Datasheet

CMOSOutputBuffers

14-BitADCData

ADS414x

CLKOUT

D12

D13

CLKIN

D0_In

D1_In

D2_In

D12_In

D13_In

UseExternalClockBuffer

(>200MSPS)

Useshorttracesbetween

ADCoutputandreceiverpins(1to2inches).

Flip-Flops

Receiver(FPGA,ASIC,etc.)

InputClock

ADS4122, ADS4125

ADS4142, ADS4145

SBAS520A –FEBRUARY 2011– REVISED MARCH 2011

www.ti.com

Figure 117. Using the CMOS Data Outputs

CMOS Interface Power Dissipation

With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every

output pin. The maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock

cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined

by the average number of output bits switching, which is a function of the sampling frequency and the nature of

the analog input signal.

Digital Current as a Result of CMOS Output Switching = C

× DRVDD × (N × f

AVG

)

where:

= load capacitance,

N × F

AVG

= average number of output bits switching. (1)

Figure 94 details the current across sampling frequencies at 2 MHz analog input frequency.

Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145