Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal HTQFP 80

FEATURES

APPLICATIONS

DESCRIPTION

12−Bit

ADC

PLL

S/H S erializer

1x ADCLK

6x ADCLK

IN1

ADCLK

IN1

OUT1

12−Bit

ADC

S/H

S erializer

IN2

OUT2

12−Bit

ADC

S/H S erializer

IN3

OUT3

LCL K

ADCLK

12x ADCLK

12−Bit

ADC

S/H S erializer

IN4

OUT4

12−Bit

ADC

S/H

S erializer

IN5

OUT5

12−Bit

ADC

S/H

S erializer

IN6

OUT6

12−Bit

ADC

S/H

S erializer

IN7

OUT7

12−Bit

ADC

S/H S erializer

Re feren ce

IN8

REF

IN T/EXT

REF

OUT8

Registers

SCLK

SDATA

Con trol

RESET

ADS5270

www.ti.com

............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009

8-Channel, 12-Bit, 40MSPS Analog-to-Digital Converter

with Serial LVDS Interface

An integrated phase lock loop (PLL) multiplies the

incoming ADC sampling clock by a factor of 12. This

• Maximum Sample Rate: 40MSPS

high-frequency LVDS clock is used in the data

• 12-Bit Resolution

serialization and transmission process. The word

output of each internal ADC is serialized and

• No Missing Codes

transmitted either MSB or LSB first. In addition to the

• Total Power Dissipation:

eight data outputs, a bit clock and a word clock are

Internal Reference: 888mW

also transmitted. The bit clock is at 6x the speed of

External Reference: 822mW

the sampling clock, whereas the word clock is at the

• CMOS Technology

same speed of the sampling clock.

• Simultaneous Sample-and-Hold

The ADS5270 provides internal references, or can

• 70.5dB SNR at 10MHz IF

optionally be driven with external references. Best

performance can be achieved through the internal

• 3.3V Digital/Analog Supply

reference mode.

• Serialized LVDS Outputs

The device is available in a TQFP-80 PowerPAD

• Integrated Frame and Bit Patterns

package and is specified over a – 40 ° C to +85 ° C

• Option to Double LVDS Clock Output Currents

operating range.

• Four Current Modes for LVDS

• Pin- and Format-Compatible Family

• TQFP-80 PowerPAD™ Package

• Portable Ultrasound Systems

• Tape Drives

• Test Equipment

• Optical Networking

The ADS5270 is a high-performance, 40MSPS,

8-channel analog-to-digital converter (ADC). Internal

references are provided, simplifying system design

requirements. Low power consumption allows for the

highest of system integration densities. Serial LVDS

(low-voltage differential signaling) outputs reduce the

number of interface lines and package size.

Summary of content (31 pages)

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ADS5270 www.ti.com...............................................................................................................................................
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ADS5270 SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
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ADS5270 www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009 RECOMMENDED OPERATING CONDITIONS ADS5270 MIN TYP MAX UNITS 3.0 3.3 3.6 V SUPPLIES AND REFERENCES Analog Supply Voltage, AVDD Output Driver Supply Voltage, LVDD 3.0 3.3 3.6 V REFT — External Reference Mode 1.825 1.95 2.0 V REFB — External Reference Mode 0.9 0.95 1.
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ADS5270 SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
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ADS5270 www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009 ELECTRICAL CHARACTERISTICS (continued) TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.
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ADS5270 SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com AC CHARACTERISTICS TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
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ADS5270 www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009 LVDS DIGITAL DATA AND CLOCK OUTPUTS Test conditions at IO = 3.5mA, RLOAD = 100Ω, and CLOAD = 6pF. IO refers to the current setting for the LVDS buffer. RLOAD is the differential load resistance between the LVDS pair.
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ADS5270 SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com LVDS TIMING DIAGRAM (PER ADC CHANNEL) Sample n Sample n + 6 Input 1 t SAMPLE ADCLK tS 2 LCLKP 6X ADCLK LCLK N OUTP SERIAL DATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 OUTN Sample n data ADCLKP 1X ADCLK ADCLKN tD(A) tPROP 6.
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ADS5270 www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009 LVDS TIMING DIAGRAM (PER ADC CHANNEL) (continued) POWER-DOWN TIMING 1µs 500µs PD Device Fully Powers Down Device Fully Powers Up NOTE: The shown power−up time is based on 1µF bypass capacitors on the reference pins. See the Theory of Operation section for details.
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ADS5270 SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com SERIAL INTERFACE REGISTERS ADDRESS DATA D7 D6 D5 D4 0 0 0 0 0 0 0 0 0 0 D2 LVDS BUFFERS (Register 0) All Data Outputs 0 0 Normal ADC Output (default after reset) 0 1 Deskew Pattern 1 0 Sync Pattern 1 1 Custom Pattern 0 Output Current in LVDS = 3.
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ADS5270 www.ti.com...............................................................................................................................................
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ADS5270 SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.
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ADS5270 www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009 DEFINITION OF SPECIFICATIONS Analog Bandwidth Minimum Conversion Rate The analog input frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3dB. This is the minimum sampling rate where the ADC still works.
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ADS5270 SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS Typical values are at TA = +25C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
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ADS5270 www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = +25C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
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ADS5270 SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) Typical values are at TA = +25C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
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ADS5270 www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009 THEORY OF OPERATION OVERVIEW The ADS5270 is an 8-channel, high-speed, CMOS ADC. It consists of a high-performance sample-and-hold circuit at the input, followed by a 12-bit ADC. The 12 bits given out by each channel are serialized and sent out on a single pair of pins in LVDS format.
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ADS5270 SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com Figure 16 shows a detailed RLC model of the sample-and-hold circuit. The circuit operates in two phases. In the sample phase, the input is sampled on two capacitors that are nominally 4pF.
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ADS5270 www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009 REFERENCE CIRCUIT DESIGN The digital beam-forming algorithm relies on gain matching across all receiver channels. A typical system would have about 12 octal ADCs on the board.
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ADS5270 SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com however, is determined by the rising edge of the external clock and is not affected by jitter in the PLL.
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ADS5270 www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009 RESET It is recommended that the isolation be maintained onboard by using separate supplies to drive AVDD and LVDD, as well as separate ground planes for AVSS and LVSS. After the supplies have stabilized, it is necessary to give the device an active RESET pulse.
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ADS5270 SBAS293F – JANUARY 2004 – REVISED JANUARY 2009............................................................................................................................................... www.ti.com Revision History Changes from Revision E (September 2005) to Revision F ........................................................................................... Page • Updated Absolute Maximum Ratings table: added entries for Digital Input Pins, Set 1 and Set 2 and added footnote 3....
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ADS5270 www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009 • • • • • • • • • • • • • • • • • • • • • • • • • • • • Changed Typical Characteristics conditions to include TA = +25°C and ISET = 56.2kΩ. ..................................................... Changed Figure 13. ........................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS5270IPFPT Package Package Pins Type Drawing HTQFP PFP 80 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 15.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.0 1.5 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS5270IPFPT HTQFP PFP 80 250 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.