Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal VQFN 64

12-Bit

ADC

PLL

Serializer

1xADCLK

6xADCLK

IN1

OUT1

LCLK

ADCLK

12xADCLK

12-Bit

ADC

Serializer

Digital

Reference

IN8

REF

INT/

EXT

REF

OUT8

SET

Registers

SDATA

RESET

SCLK

ADC

Control

Clock

Buffer

(ADCLK)

CLK

(AVSS)

CLK

AVDD

(3.3V)

LVDD

(1.8V)

Power-

Down

TestPatterns

DriveCurrent

OutputFormat

DigitalGain

(0dBto12dB)

Channels

2to7

ADS5281

ADS5282

www.ti.com

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

12-Bit Octal-Channel ADC Family Up to 65MSPS

Check for Samples: ADS5281, ADS5282

FEATURES

DESCRIPTION

The ADS528x is a family of high-performance, low-

234

• Speed and Resolution Grades:

power, octal channel analog-to-digital converters

– ADS5281: 12-bit, 50MSPS

(ADCs). Available in either a 9mm × 9mm QFN

– ADS5282: 12-bit, 65MSPS

package or an HTQFP-80 package, with serialized

low-voltage differential signaling (LVDS) outputs and

• Power Dissipation:

a wide variety of programmable features, the

– 48mW/Channel at 30MSPS

ADS528x is highly customizable for a diversity of

– 55mW/Channel at 40MSPS

applications and offers an unprecedented level of

system integration. An application note, XAPP774

– 64mW/Channel at 50MSPS

(available at www.xilinx.com), describes how to

– 77mW/Channel at 65MSPS

interface the serial LVDS outputs of TI's ADCs to

• 70dBFS SNR at 10MHz IF

Xilinx

field-programmable gate arrays (FPGAs). The

ADS528x family is specified over the industrial

• Analog Input Full-Scale Range: 2V

temperature range of –40°C to +85°C.

• Low-Frequency Noise Suppression Mode

• 6dB Overload Recovery In One Clock

• External and Internal (Trimmed) Reference

• 3.3V Analog Supply, 1.8V Digital Supply

• Single-Ended or Differential Clock:

– Clock Duty Cycle Correction Circuit (DCC)

• Programmable Digital Gain: 0dB to 12dB

• Serialized DDR LVDS Output

• Programmable LVDS Current Drive, Internal

Termination

• Test Patterns for Enabling Output Capture

• Straight Offset Binary or Two's Complement

Output

• Package Options:

– 9mm × 9mm QFN-64

– HTQFP-80 PowerPAD™ Compatible with

ADS527x Family

APPLICATIONS

• Medical Imaging

• Wireless Base-Station Infrastructure

• Test and Measurement Instrumentation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments, Inc.

3Xilinx is a registered trademark of Xilinx, Inc.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (50 pages)

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ADS5281 ADS5282 www.ti.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 RECOMMENDED OPERATING CONDITIONS (1) ADS528x PARAMETER MIN TYP MAX UNIT V SUPPLIES, ANALOG INPUTS, AND REFERENCE VOLTAGES AVDD Analog supply voltage 3.0 3.3 3.6 LVDD Digital supply voltage 1.7 1.8 1.9 Differential input voltage range Input common-mode voltage V 2 VPP VCM ± 0.05 V REFT External reference mode 2.5 V REFB External reference mode 0.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com DIGITAL CHARACTERISTICS DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level '0' or '1'. At CLOAD = 5pF (1), IOUT = 3.5mA (2), RLOAD = 100Ω (2), and no internal termination, unless otherwise noted. ADS528x PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 1.4 V Low-level input voltage 0.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS (1) Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless otherwise noted.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS (BY DEVICE) (1) Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless otherwise noted.
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ADS5281 ADS5282 www.ti.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com Table 2.
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ADS5281 ADS5282 www.ti.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com Table 3.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 LVDD (1.8V) AVDD (3.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 LVDS OUTPUT TIMING CHARACTERISTICS (1) (2) Typical values are at +25°C, minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX = +85°C, sampling frequency = as specified, CLOAD = 5pF (3), IOUT = 3.5mA, RLOAD = 100Ω (4), and no internal termination, unless otherwise noted.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com LVDS OUTPUT TIMING CHARACTERISTICS PARAMETER (1) TIMINGS WHEN USING REGISTER 0xE3 (2) At 40 MSPS TEST CONDITIONS MIN Data setup time Data valid (3) to zero-crossing of LCLKp 0.60 Data hold time Zero-crossing of LCLKP to data becoming invalid (3) 0.92 Clock propagation delay Input clock (ADCLK) rising edge cross-over to output clock (ADCLK) rising edge crossover (1) (2) (3) TYP MAX 12 14.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 POWER-DOWN TIMING 1ms tWAKE PD Device Fully Powers Down Device Fully Powers Up Power-up time shown is based on 1μF bypass capacitors on the reference pins. tWAKE is the time it takes for the device to wake up completely from power-down mode. The ADS528x has two power-down modes: complete power-down mode and partial power-down mode. The device can be configured in partial power-down mode through a register setting.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com SERIAL INTERFACE The ADS528x has a set of internal registers that can be accessed through the serial interface formed by pins CS (chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data).
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 SERIAL REGISTER MAP Table 4. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 00 X X X X X X X (2) (3) (4) D0 NAME X RST Self-clearing software RESET. Inactive PDN_CH<8:1> Channel-specific ADC powerdown mode. Inactive PDN_PARTIAL Partial power-down mode (fast recovery from power-down).
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com Table 4. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE(1) (2) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 1 1 D0 NAME X DIFF_CLK X EN_DCC (3) (4) (continued) DESCRIPTION Differential clock mode. Enables the duty-cycle correction circuit. X 1 X X Singleended clock Disabled EXT_REF_VCM Drives the external reference mode through the VCM pin.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 DESCRIPTION OF SERIAL REGISTERS SOFTWARE RESET ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 00 D0 NAME X RST Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears to '0'.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com All three drive strengths (bit clock, frame clock, and data) are programmed using sets of three bits. Table 5 shows an example of how the drive strength of the bit clock is programmed (the method is similar for the frame clock and data drive strengths). Table 5. Bit Clock Drive Strength (1) (1) ILVDS_LCLK<2> ILVDS_LCLK<1> ILVDS_LCLK<0> LVDS DRIVE STRENGTH FOR LCLKP AND LCLKN 0 0 0 3.5mA (default) 0 0 1 2.5mA 0 1 0 1.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 LOW-FREQUENCY NOISE SUPPRESSION MODE ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 14 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X X X X X LFNS_CH<8:1> The low-frequency noise suppression mode is specifically useful in applications where good noise performance is desired in the frequency band of 0MHz to 1MHz (around dc).
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 CLOCK, REFERENCE, AND DATA OUTPUT MODES ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 1 1 X D1 D0 NAME X DIFF_CLK EN_DCC 42 1 X 1 X 1 1 1 1 EXT_REF_VCM X PHASE_DDR<1:0> X X BTC_MODE MSB_FIRST 46 1 1 X 1 X EN_SDR 1 1 FALL_SDR INPUT CLOCK The ADS528x is configured by default to operate with a single-ended input clock—CLKP is driven by a CMOS clock and CLKN is tied to '0'.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com BIT CLOCK PROGRAMMABILITY The output interface of the ADS528x is normally a DDR interface, with the LCLK rising edge and falling edge transitions in the middle of alternate data windows. This default phase is shown in Figure 1. ADCLKP LCLKP OUTP Figure 1. Default Phase of LCLK The phase of LCLK can be programmed relative to the output frame clock and data using bits PHASE_DDR<1:0>. The LCLK phase modes are shown in Figure 2.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12x times the input clock, or twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two manners shown in Figure 3.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50% clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless otherwise noted.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50% clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50% clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50% clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50% clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50% clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS528x devices are a family of 8-channel, high-speed, CMOS ADCs. The 12 bits given out by each channel are serialized and sent out on a single pair of pins in LVDS format. All eight channels of the ADS528x operate from a single clock (ADCLK). The sampling clocks for each of the eight channels are generated from the input clock using a carefully matched clock buffer tree.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 5nH to 9nH (TQFP-80) 2nH to 3nH (QFN-64) IN OUT INP 1.5pF to 2.5pF 5W to 10W 15W to 25W 1W IN 1.5pF to 2.4pF 15W to 30W OUT IN 1000W to 1440W OUT OUT OUTP 0.2pF to 0.3pF IN OUTN 1000W to 1440W 16W to 32W 5W to 10W 15W to 25W IN 5nH to 9nH (TQFP-80) 2nH to 3nH (QFN-64) OUT 1.5pF to 2.4pF 15W to 30W IN OUT INN 1.5pF to 2.5pF Switches that are ON in SAMPLE phase. 1W Switches that are ON in HOLD phase.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com Driving Circuit At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps to minimize this mismatch, and good performance is obtained for high-frequency input signals. An additional termination resistor pair is required between the two transformers, as shown in Figure 37.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 CLOCK INPUT The eight channels on the device operate from a single ADCLK input. To ensure that the aperture delay and jitter are the same for all channels, a clock tree network is used to generate individual sampling clocks to each channel. The clock paths for all the channels are matched from the source point to the sampling circuit. This architecture ensures that the performance and timing for all channels are identical.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 www.ti.com PLL OPERATION ACROSS SAMPLING FREQUENCY The ADS528X uses a PLL for generating the high speed bit clock (LCLK), the frame clock (ADCLK) & internal clocks for the serializer operation. To enable operation across the entire frequency range, the PLL is automatically configured to one of four states, depending on the sampling clock frequency range.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 resistor at ISET reduces the reference bias current and thereby scales down the device operating power. However, it is recommended that the external resistor be within 10% of the specified value of 56.2kΩ so that the internal bias margins for the various blocks are proper. The device also supports the use of external reference voltages. There are two methods to force the references externally.
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ADS5281 ADS5282 SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 Smaller effective inductance of the supply and ground pins leads to better noise suppression. For this reason, multiple pins are used to drive each supply and ground. It is also critical to ensure that the impedances of the supply and ground lines on the board are kept to the minimum possible values.
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ADS5281 ADS5282 www.ti.com SBAS397I – DECEMBER 2006 – REVISED JUNE 2012 REVISION HISTORY Changes from Revision G (March 2008) to Revision H Page • Changed second table and conditions in the Initialization Registers section ....................................................................... 3 • Changed In Input Common-Mode Current section, changed initialization register 5 to initialization registers 1 and 5 to reflect change in Initialization Registers table ......................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Jan-2012 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS5281IPFPR HTQFP PFP 80 1000 330.0 24.4 15.0 15.0 1.5 20.0 24.0 Q2 ADS5281IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS5281IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS5281IPFPR HTQFP PFP 80 1000 367.0 367.0 45.0 ADS5281IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS5281IRGCT VQFN RGC 64 250 336.6 336.6 28.6 ADS5282IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS5282IRGCT VQFN RGC 64 250 336.6 336.6 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.