Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Internal HTQFP 64

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FEATURES DESCRIPTION

APPLICATIONS

ADS5500

SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007

14-Bit, 125Msps ANALOG-TO-DIGITAL CONVERTER

• 14-Bit Resolution

The ADS5500 is a high-performance, 14-bit, 125

Msps analog-to-digital converter (ADC). To provide a

• 125 Msps Sample Rate

complete converter solution, it includes a

• High SNR: 71.2 dBFS at 100-MHz f

high-bandwidth linear sample-and-hold stage (S&H)

• High SFDR: 82 dBc at 100-MHz f

and internal reference. Designed for applications

• 2.3-V

Differential Input Voltage demanding the highest speed and highest dynamic

performance in little space, the ADS5500 has

• Internal Voltage Reference

excellent power consumption of 578 mW at 3.3-V

• 3.3-V Single-Supply Voltage

single-supply voltage. This allows an even higher

• Analog Power Dissipation: 578 mW

system integration density. The provided internal

reference simplifies system design requirements.

• Serial Programming Interface

Parallel CMOS-compatible output ensures seamless

• TQFP-64 PowerPAD™ Package

interfacing with common logic.

• Recommended Amplifiers:

The ADS5500 is available in a 64-pin TQFP

OPA695, OPA847, THS3201, THS3202,

PowerPAD™ package and in both a commercial and

THS4503, THS4509, THS9001

industrial temperature grade device.

ADS5500 PRODUCT FAMILY

• Wireless Communication

80 Msps 105 Msps 125 Msps

– Communication Receivers

12 Bit ADS5522 ADS5521 ADS5520

– Base Station Infrastructure

14 Bit ADS5542 ADS5541 ADS5500

• Test and Measurement Instrumentation

• Single and Multichannel Digital Receivers

• Communication Instrumentation

– Radar, Infrared

• Video and Imaging

• Medical Equipment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 14-Bit, 125Msps ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION • • • • • • • • • • • The ADS5500 is a high-performance, 14-bit, 125 Msps analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 RECOMMENDED OPERATING CONDITIONS (continued) MIN Clock duty cycle (see Figure 49 for more information) NOM MAX UNIT 50% Open free-air temperature range 0 70 –40 85 °C ELECTRICAL CHARACTERISTICS Typ values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) Typ values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) Typ values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TIMING CHARACTERISTICS NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing matches closely with the specified values. Figure 1. Timing Diagram TIMING CHARACTERISTICS (1) (2) Typ values given at TA = 25°C, min and max specified over the full recommended operating temperature range, sampling rate = 125 Msps, 50% clock duty cycle, AVDD = DRVDD = 3.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TIMING CHARACTERISTICS (continued) Typ values given at TA = 25°C, min and max specified over the full recommended operating temperature range, sampling rate = 125 Msps, 50% clock duty cycle, AVDD = DRVDD = 3.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 Figure 3. DATA Communication is 2-Byte, MSB First Figure 4. Serial Programming Interface Timing Diagram Table 1.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 Table 3. Data Format Select (DFS Table) DFS-PIN VOLTAGE (VDFS) 2 V DFS t 12 AV DD DATA FORMAT CLOCK OUTPUT POLARITY Straight Binary Data valid on rising edge 4 12 5 AV DD t V DFS t 12 AV DD Two's Complement Data valid on rising edge 7 12 AV DD t V DFS t 8 12 AV DD Straight Binary Data valid on falling edge Two's Complement Data valid on falling edge V DFS u 10 12 AV DD PIN CONFIGURATION PIN ASSIGNMENTS TERMINAL NO.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 PIN CONFIGURATION (continued) PIN ASSIGNMENTS (continued) TERMINAL NAME NO. NO. OF PINS I/O DRGND 1, 42, 48, 50, 57, 59 6 I Output driver ground INP 19 1 I Differential analog input (positive) INM 20 1 I Differential analog input (negative) REFP 29 1 O Reference voltage (positive); 1-µF capacitor to GND REFM 30 1 O Reference voltage (negative); 1-µF capacitor to GND IREF 31 1 I Current set; 56.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 Offset Error The offset error is the difference, given in number of LSBs, between the ADC's actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. Effective Number of Bits (ENOB) The ENOB is a measure of a converter's performance as compared to the theoretical limit based on quantization noise. ENOB + SINAD * 1.76 6.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted 12 SPECTRAL PERFORMANCE (FFT for 2-MHz Input Signal) SPECTRAL PERFORMANCE (FFT for 15-MHz Input Signal) Figure 5. Figure 6.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted SPECTRAL PERFORMANCE (FFT for 150-MHz Input Signal) SPECTRAL PERFORMANCE (FFT for 225-MHz Input Signal) Figure 11. Figure 12. SPECTRAL PERFORMANCE (FFT for 300-MHz Input Signal) TWO-TONE INTERMODULATION Figure 13.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted 14 DIFFERENTIAL NONLINEARITY (DNL) INTEGRAL NONLINEARITY (INL) Figure 17. Figure 18. SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY Figure 19. Figure 20.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE Figure 21. Figure 22. AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE Figure 23. Figure 24.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted 16 TOTAL POWER DISSIPATION vs SAMPLING FREQUENCY SIGNAL-TO-NOISE RATIO AND SPURIOUS-FREE DYNAMIC RANGE vs TEMPERATURE Figure 25. Figure 26. AC PERFORMANCE vs INPUT AMPLITUDE AC PERFORMANCE vs INPUT AMPLITUDE Figure 27.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted AC PERFORMANCE vs INPUT AMPLITUDE OUTPUT NOISE HISTOGRAM Figure 29. Figure 30. AC PERFORMANCE vs CLOCK AMPLITUDE WCDMA CARRIER Figure 31. Figure 32.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted SIGNAL-TO-NOISE RATIO (SNR) WITH DLL ON Figure 33. SIGNAL-TO-NOISE RATIO (SNR) WITH DLL OFF Figure 34.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted SPURIOUS-FREE DYNAMIC RANGE (SFDR) WITH DLL ON Figure 35. SPURIOUS-FREE DYNAMIC RANGE (SFDR) WITH DLL OFF Figure 36.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted SECOND HARMONIC (HD2) WITH DLL ON Figure 37. SECOND HARMONIC (HD2) WITH DLL OFF Figure 38.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps, DLL On, and 3-V differential clock unless otherwise noted THIRD HARMONIC (HD3) WITH DLL ON Figure 39. THIRD HARMONIC (HD3) WITH DLL OFF Figure 40.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 APPLICATION INFORMATION THEORY OF OPERATION The ADS5500 is a low-power, 14-bit, 125 Msps, CMOS, switched capacitor, pipeline ADC that operates from a single 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 can be selected depending on the application. An RF gain block amplifier, such as TI's THS9001, can also be used with an RF transformer for very high input frequency applications. The THS4503 is a recommended differential input/output amplifier. Table 4 lists the recommended amplifiers. Figure 42.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 Table 4.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state and only the internal reference remains on to reduce the power-up time. The power-down mode reduces power dissipation to approximately 180 mW. REFERENCE CIRCUIT The ADS5500 has built-in internal reference generation, requiring no external circuitry on the printed circuit board (PCB).
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 DLL OFF mode described in the Serial Interface Programming section. The Typical Performance Curves show the performance obtained in both modes of operation: DLL ON (default) and DLL OFF. In either of the two modes, the device enters power-down mode if no clock or slow clock is provided. The limit of the clock frequency where the device functions properly with default settings is ensured to be over 2 MHz. OUTPUT INFORMATION Figure 49.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay (td) that results in the desired setup or hold time. Use either of the following equations to calculate the value of td. Desired setup time = td– tSTART Desired hold time = tEND– td Table 5. Timing Characteristics at Additional Sampling Frequencies (DLL ON) FS (Msps) tsu (ns) MIN TYP 105 2.2 80 65 th (ns) MAX MIN TYP 2.8 2.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 Write Write Write Write Write D000h (Address D, Data 000) E000h (Address E, Data 804) 0000h (Address 0, Data 000) 1000h (Address 1, Data 000) F000h (Address F, Data 000). 2. NOTE: This procedure is only required if a RESET pulse is not provided to the device. 3.
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ADS5500 www.ti.com SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007 REVISION HISTORY REVISION DATE DESCRIPTION 0.0 12/03 Preliminary data sheet released 1.0 03/04 Data sheet updated to reflect RTM silicon 2.0 09/05 Added information regarding thermal pad size and thermal characteristics of the package. Removed input current from Absolute Maximum Ratings table. Updated specifications to AGND and DRGND. Added notes regarding the input voltage overstress requirements.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS5500IPAPR Package Package Pins Type Drawing HTQFP PAP 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS5500IPAPR HTQFP PAP 64 1000 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.