ADS5542 SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 14-Bit, 80 MSPS Analog-To-Digital Converter FEATURES • • • • • • • • • 14-Bit Resolution 80 MSPS Sample Rate High SNR: 72.9 dBFS at 100 MHz fIN High SFDR: 88 dBc at 100 MHz fIN 2.3-VPP Differential Input Voltage Internal Voltage Reference 3.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 AVDD DRVDD CLK+ CLK− Timing Circuitry 14-Bit Pipeline ADC Core VIN+ S&H VIN− CM Internal Reference CLKOUT Digital Error Correction D0 . . . D13 Output Control OVR DFS Control Logic Serial Programming Register AGND SEN SDATA ADS5542 SCLK DRGND This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT Analog supply voltage, AVDD 3 3.3 3.6 V Output driver supply voltage, DRVDD 3 3.3 3.6 V SUPPLIES ANALOG INPUT Differential input range Input common-mode voltage, VCM 2.3 (1) 1.45 1.55 VPP 1.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and –1dBFS differential input, unless otherwise noted PARAMETER CONDITIONS MIN TYP 25°C to 85°C 72.7 74.3 Full temp range 71.5 74.0 25°C to 85°C 71.5 73.5 Full temp range 70.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 TIMING CHARACTERISTICS (1) (2) Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 RESET TIMING CHARACTERISTICS Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 tSLOADS SEN tSLOADH tWSCLK tWSCLK tSCLK SCLK tsu(D) SDATA th(D) MSB LSB MSB LSB 16 x M Figure 4. Serial Programming Interface Timing Diagram Table 1.
ADS5542 www.ti.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 PIN CONFIGURATION (continued) PIN ASSIGNMENTS TERMINAL NO. OF PINS I/O AVDD 5, 7, 9, 15, 22, 24, 26, 28, 33, 34, 37, 39 12 I Analog power supply AGND 6, 8, 12–14, 16, 18, 21, 23, 25, 27, 32, 36, 38 14 I Analog ground (PowerPAD is connected to analog ground.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 DEFINITION OF SPECIFICATIONS Offset Error Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay The delay in time between the falling edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 Total Harmonic Distortion (THD) Two-Tone Intermodulation Distortion (IMD3) THD is the ratio of the power of the fundamental (PS) to the power of the first eight harmonics (PD). P THD + 10Log 10 S PD IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPS and 3-V differential clock, unless otherwise noted SPECTRAL PERFORMANCE (FFT for 4 MHz Input Signal) SPECTRAL PERFORMANCE (FFT for 16 MHz Input Signal) 0 0 SFDR = 92.1dBc SNR = 74.0dBFS THD = 88.4dBc SINAD = 73.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPS and 3-V differential clock, unless otherwise noted SPECTRAL PERFORMANCE (FFT for 150 MHz Input Signal) SPECTRAL PERFORMANCE (FFT for 220 MHz Input Signal) 0 0 Magnitude − dB −20 −40 −60 −80 SFDR = 78.4dBc SNR = 70.7dBFS THD = 75.8dBc SINAD = 69.8dBFS −20 Magnitude − dB SFDR = 88.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPS and 3-V differential clock, unless otherwise noted DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY 1.0 2.0 f IN = 10MHz AIN = −0.5dBFS 0.8 0.6 1.0 INL − LSB DNL − LSB 0.4 0.2 0 −0.2 −0.4 0.5 0 −0.5 −1.0 −0.6 −1.5 −0.8 −1.0 −2.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPS and 3-V differential clock, unless otherwise noted AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE 95 fIN = 150MHz SFDR SFDR − dBc SFDR − dBc 95 90 85 85 80 75 SNR − dBFS SNR − dBFS 80 fIN = 70MHz SFDR 90 SNR 70 65 SNR 75 70 65 3.0 3.1 3.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, AVDD = DRVDD = 3.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, and 3-V differential clock, unless otherwise noted SIGNAL-TO-NOISE RATIO (SNR) 74 100 70 74 69 90 72 73 80 71 72 60 70 74 69 50 68 71 73 72 66 70 40 69 68 66 65 67 30 66 74 71 20 72 73 68 70 64 65 67 69 66 63 10 50 100 150 200 Input Frequency (MHz) Figure 35.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, AVDD = DRVDD = 3.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 APPLICATION INFORMATION THEORY OF OPERATION The ADS5542 is a low-power, 14-bit, 80 MSPS, CMOS, switched capacitor, pipeline ADC that operates from a single 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once the signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 This differential input topology produces a high level of ac-performance for high sampling rates. It also results in a very high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersampling applications. The ADS5542 requires each of the analog inputs (INP, INM) to be externally biased around the common-mode level of the internal circuitry (CM, pin 17).
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 Figure 39 illustrates how RIN and CIN can be placed to isolate the signal source from the switching inputs of the ADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended that these components be included in the ADS5542 circuit layout when any of the amplifier circuits discussed previously are used. The components allow fine-tuning of the circuit performance.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 POWER-SUPPLY SEQUENCE The preferred power-up sequence is to ramp AVDD first, followed by DRVDD, including a simultaneous ramp of AVDD and DRVDD. In the event that DRVDD ramps up first in the system, care must be taken to ensure that AVDD ramps up within 10 ms. Optionally, it is recommended to put a 2-kΩ resistor from REFP (pin 29) to AVDD as shown in Figure 41. This helps to make the device more robust to power supply ramp-up timings.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 CLOCK INPUT The ADS5542 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. The common-mode voltage of the clock inputs is set internally to CM (pin 17) using internal 5-kΩ resistors that connect CLKP (pin 10) and CLKM (pin 11) to CM (pin 17), as shown in Figure 43. CM CM 5 kW 5 kW CLKM CLKP 6 pF 3 pF 3 pF Figure 43.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 SFDR − dBc 100 fIN = 20MHz 95 SFDR 90 85 SNR − dBFS 80 75 SNR 70 65 60 35 40 45 50 55 60 65 Clock Duty Cycle − % Figure 46. AC Performance vs Clock Duty Cycle Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When using a sinusoidal clock, the clock jitter further improves as the amplitude is increased.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive overdrive, the output code is 0x3FFF in straight offset binary output format, and 0x1FFF in 2's complement output format. For a negative input overdrive, the output code is 0x0000 in straight offset binary output format and 0x2000 in two's complement output format.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 Applying a RESET signal is absolutely essential to set the internal registers to their default states for normal operation. If the hardware RESET function is not used in the system, the RESET pin must be tied to ground and it is necessary to write the default values to the internal registers through the serial programming interface. The following registers must be written in this order.
ADS5542 www.ti.com SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 Table 7. Revision History Added notes regarding the input voltage overstress requirements in the absolute maximum ratings table Changed minimum recommended sampling rate to 2 MSPS. Added timing parameters - output clock jitter, wakeup time, output clock rise and fall time, Tpdi and timings across Fs. Clarified output capture test modes. Pin table info added - RESET pin, note on OE, SEN, SDATA and SCLK pins Updated the definitions section.
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