Datasheet

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ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
PIN CONFIGURATION (continued)
PIN ASSIGNMENTS
TERMINAL
NO. OF
NAME NO. PINS I/O DESCRIPTION
5, 7, 9, 15, 22,
AV
DD
24, 26, 28, 33, 12 I Analog power supply
34, 37, 39
6, 8, 12–14,
16, 18, 21, 23,
A
GND
14 I Analog ground (PowerPAD is connected to analog ground.)
25, 27, 32, 36,
38
DRV
DD
49, 58 2 I Output driver power supply
1, 42, 48, 50,
DR
GND
6 I Output driver ground
57, 59
INP 19 1 I Differential analog input (positive)
INM 20 1 I Differential analog input (negative)
REFP 29 1 O Reference voltage (positive); 1- µ F capacitor in series with a 1- Ω resistor to GND
REFM 30 1 O Reference voltage (negative); 1- µ F capacitor in series with a 1- Ω resistor to GND
IREF 31 1 I Current set; 56.2-k Ω resistor to GND; do not connect capacitors
CM 17 1 O Common-mode output voltage
RESET 35 1 I Reset (active high), Internal 200-k Ω resistor to AV
DD
(1)
OE 41 1 I Output enable (active high)
(2)
DFS 40 1 I Data format and clock out polarity select
(3) (2)
CLKP 10 1 I Data converter differential input clock (positive)
CLKM 11 1 I Data converter differential input clock (negative)
SEN 4 1 I Serial interface chip select
(2)
SDATA 3 1 I Serial interface data
(2)
SCLK 2 1 I Serial interface clock
(2)
D0 (LSB) to 44-47, 51-56,
14 O Parallel data output
D13 (MSB) 60-63
OVR 64 1 O Over-range indicator bit
CLKOUT 43 1 O CMOS clock out in sync with data
(1) If unused, the RESET pin should be tied to AGND. See the serial programmine interface section for details.
(2) Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins
must also run off the same supply voltage as DRVDD.
(3) Table 3 defines the voltage levels for each mode selectable via the DFS pin.
10
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