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RESET TIMING CHARACTERISTICS
RESET (Pin 35)
t
1
10 ms
t
2
2 ms t
3
2 ms
SEN Active
Power Supply
(AV
DD
, DRV
DD
)
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
A3
ADDRESS
SDATA
MSB
DATA
A2 A1 A0 D11 D10 D9 D0
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
Typical values given at T
A
= 25 ° C, min and max specified over the full recommended operating temperature range, AV
DD
=
DRV
DD
= 3.3 V, and 3-V
PP
differential clock, unless otherwise noted
PARAMETER DESCRIPTION MIN TYP MAX UNIT
Switching Specification
t
1
Power-on delay Delay from power-on of AV
DD
and DRV
DD
to RESET pulse 10 ms
active
t
2
Reset pulse width Pulse width of active RESET signal 2 µ s
t
3
Register write delay Delay from RESET disable to SEN active 2 µ s
Power-up time Delay from power-up of AV
DD
and DRV
DD
to output stable 40 ms
Figure 2. Reset Timing Diagram
The ADS5542 has a three-wire serial interface. The ADS5542 latches serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
• Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge.
• Minimum width of data stream for a valid loading is 16 clocks.
• Data is loaded at every 16th SCLK falling edge while SEN is low.
• In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.
• Data can be loaded in multiples of 16-bit words within a single active SEN pulse.
• The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.
Figure 3. DATA Communication is 2-Byte, MSB First
7
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