Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Internal VQFN 32

FEATURES

DESCRIPTION

APPLICATIONS

ADS6125, ADS6124

ADS6123, ADS6122

SLAS560A – OCTOBER 2007 – REVISED MARCH 2008

www.ti.com

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

• Maximum Sample Rate: 125 MSPS

• 12-Bit Resolution with No Missing Codes

ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X)

is a family of 12-bit A/D converters with sampling

• 3.5 dB Coarse Gain and up to 6 dB

frequencies up to 125 MSPS. It combines high

Programmable Fine Gain for SNR/SFDR

performance and low power consumption in a

Trade-Off

compact 32 QFN package. Using an internal high

• Parallel CMOS and Double Data Rate (DDR)

bandwidth sample and hold and a low jitter clock

LVDS Output Options

buffer helps to achieve high SNR and high SFDR

even at high input frequencies.

• Supports Sine, LVCMOS, LVPECL, LVDS Clock

Inputs and Clock Amplitude Down to 400 mV

It features coarse and fine gain options that are used

to improve SFDR performance at lower full-scale

• Clock Duty Cycle Stabilizer

analog input ranges.

• Internal Reference with Support for External

Reference

The digital data outputs are either parallel CMOS or

DDR LVDS (Double Data Rate). Several features

• No External Decoupling Required for

exist to ease data capture such as — controls for

References

output clock position and output buffer drive strength,

• Programmable Output Clock Position and

and LVDS current and internal termination

Drive Strength to Ease Data Capture

programmability.

• 3.3 V Analog and 1.8 V to 3.3 V Digital Supply

The output interface type, gain, and other functions

• 32-QFN Package (5 mm × 5 mm)

are programmed using a 3-wire serial interface.

Alternatively, some of these functions are configured

• Pin Compatible 12-Bit Family (ADS612X)

using dedicated parallel pins so that the device

comes up in the desired state after power-up.

• Wireless Communications Infrastructure

ADS612X includes internal references, while

eliminating the traditional reference pins and

• Software Defined Radio

associated external decoupling. External reference

• Power Amplifier Linearization

mode is also supported.

• 802.16d/e

The devices are specified over the industrial

• Test and Measurement Instrumentation

temperature range ( – 40 ° C to 85 ° C).

• High Definition Video

• Medical Imaging

• Radar Systems

ADS612X Performance Summary

ADS6125 ADS6124 ADS6123 ADS6122

= 10 MHz (0 dB gain) 90 91 93 95

SFDR, dBc

= 170 MHz (3.5 dB gain) 78 82 83 84

= 10 MHz (0 dB gain) 71.1 71.3 71.5 71.6

SINAD, dBFS

= 170 MHz (3.5 dB gain) 67.6 69.1 69.2 69.8

Power, mW 417 374 318 285

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (67 pages)

PAGE 1
ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS FEATURES 1 • • • • • • • • • • • • Maximum Sample Rate: 125 MSPS 12-Bit Resolution with No Missing Codes 3.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. CLKP DRGND DRVDD AGND AVDD ESD damage can range from subtle performance degradation to complete device failure.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT 3 3.3 3.6 V 1.65 1.8 to 3.3 3.6 V 3 3.3 3.6 V SUPPLIES AVDD Analog supply voltage (1) DRVDD Output buffer supply voltage CMOS Interface LVDS Interface ANALOG INPUTS Differential input voltage range VIC 2 Input common-mode voltage Vpp 1.5 ± 0.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 DIGITAL CHARACTERISTICS (1) The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = 3.3 V PARAMETER ADS6125/ADS6124 ADS6123/ADS6122 TEST CONDITIONS MIN DIGITAL INPUTS PDN, SCLK, SEN & SDATA TYP MAX UNIT (2) High-level input voltage 2.4 V Low-level input voltage 0.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued) For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data sheet.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 DEVICE PROGRAMMING MODES ADS612X has several features that can be easily configured using either parallel interface control or serial interface programming. USING SERIAL INTERFACE PROGRAMMING ONLY To program using the serial interface, the internal registers must first be reset to their default values, and the RESET pin must be kept low.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 Table 3. SDATA, PDN Control Pins SDATA PDN DESCRIPTION Low Low Low High (AVDD) Normal operation High (AVDD) Low High (AVDD) High (AVDD) Standby - only the ADC is powered down Output buffers are powered down, fast wake-up time Global power down.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 SERIAL INTERFACE TIMING Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 SERIAL REGISTER MAP Table 4 provides a summary of all the modes that can be programmed through the serial interface. Table 4.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 DESCRIPTION OF SERIAL REGISTERS Each register function is explained in detail below. Table 5.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 Table 6. A4–A0 (hex) 04 D8 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Output data position control Output Clock edge control Output Clock position control 0 0 0 0 0 0 0 0 Output clock position control 0 Default output clock position after reset. The setup/hold timings for this clock position are specified in the timing specifications table.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 Table 8.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 Table 11. A4–A0 (hex) D10 0E 0 D1-D0 D0 D9 D8 D7 D4 D2 LVDS Current control D1 D0 LVDS current double LVDS Data buffer current control 1 2x LVDS Current set by LVDS Clock buffer current control 0 Default current, set by 1 2x LVDS Current set by LVDS current programming 00 3.5 mA 01 2.5 mA 10 4.5 mA 11 1.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 Table 12.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 PIN CONFIGURATION (CMOS MODE) DRVDD 1 25 OVR 26 CLKOUT 27 D6 28 D7 29 D8 30 D9 31 D10 32 D11 RHB PACKAGE (TOP VIEW) 24 D5 Bottom Pad Connected To DRGND RESET 2 23 D4 CLKP 7 18 NC CLKM 8 17 NC PDN 16 19 D0 AVDD 15 AGND 6 VCM 14 20 D1 AVDD 13 SEN 5 AGND 12 21 D2 INM 11 SDATA 4 INP 10 22 D3 AGND 9 SCLK 3 Figure 7. CMOS Mode Pinout Table 13.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 Table 13.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 PIN CONFIGURATION (LVDS MODE) DRVDD 1 25 CLKOUTM 26 CLKOUTP 27 D6_D7_M 28 D6_D7_P 29 D8_D9_M 30 D8_D9_P 31 D10_D11_M 32 D10_D11_P RHB PACKAGE (TOP VIEW) 24 D4_D5_P Bottom Pad Connected To DRGND RESET 2 23 D4_D5_M CLKP 7 18 NC CLKM 8 17 NC PDN 16 19 D0_D1_M AVDD 15 AGND 6 VCM 14 20 D0_D1_P AVDD 13 SEN 5 AGND 12 21 D2_D3_M INM 11 SDATA 4 INP 10 22 D2_D3_P AGND 9 SCLK 3 Figure 8.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 Table 14. Pin Assignments – LVDS Mode (continued) PIN NAME DESCRIPTION PIN TYPE PIN NUMBER NUMBER OF PINS CLKOUTP Differential output clock, true O 26 1 CLKOUTM Differential output clock, complement O 25 1 D0_D1_P Differential output data D0 and D1 multiplexed, true O 20 1 D0_D1_M Differential output data D0 and D1 multiplexed, complement.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 92 dBc SINAD = 71.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 80 MHz INPUT SIGNAL 0 0 SFDR = 88.2 dBc SINAD = 71.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - ADS6123 (FS= 80 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 89.34 dBc SINAD = 71.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - ADS6123 (FS= 80 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - ADS6123 (FS= 80 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - ADS6122 (FS= 65 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 90 MHz INPUT SIGNAL 0 0 SFDR = 91.8 dBc SINAD = 71.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - ADS6122 (FS= 65 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - ADS6122 (FS= 65 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT AMPLITUDE 76 110 fIN = 10.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS - LOW SAMPLING FREQUENCIES All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 COMMON PLOTS All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) POWER DISSIPATION vs SAMPLING FREQUENCY (DDR LVDS and CMOS) COMMON-MODE REJECTION RATIO vs FREQUENCY 0.8 0.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 Contour Plots Across Input and Sampling Frequencies (continued) Figure 87. SNR Contour (No gain, FS = 2 VPP) Figure 88. SNR Contour (with 3.5 dB Coarse gain, FS = 1.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 APPLICATION INFORMATION THEORY OF OPERATION ADS612X is a family of low power 12-bit pipeline ADC in a CMOS process up to 125 MSPS sampling frequency. It is based on switched capacitor technology and runs off a single 3.3-V supply. The conversion process is initiated by a rising edge of the external input clock.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 1 0 Magnitude − dB −1 −2 −3 −4 −5 −6 −7 0 100 200 300 400 500 600 fIN − Input Frequency − MHz G080 Figure 90. ADC Analog Input Bandwidth Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 9 C − Capacitance − pF 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 f − Frequency − MHz 600 G084 Figure 92. ADC Input Capacitance, Cin Using RF-Transformer Based Drive Circuits Figure 93 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that can be used for low input frequencies (about 100 MHz).
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 5W 0 .1mF INP 50 W 50 W 0 .1mF 50 W 50 W 5W INM 1:1 1:1 VCM Figure 94. Two Transformer Drive Circuit Using Differential Amplifier Drive Circuits Figure 95 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to differential output that can be interface to the ADC analog input pins.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 Input Common-Mode To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC sinks a common-mode current in the order of 180 µA (at 125 MSPS). Equation 1 describes the dependency of the common-mode current and the sampling frequency.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 COARSE GAIN and PROGRAMMABLE FINE GAIN ADS612X includes gain settings that can be used to get improved SFDR performance (compared to 0 dB gain mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 15. The coarse gain is a fixed setting of 3.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 CLOCK INPUT The clock inputs of the ADS612X can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with little or no difference in performance between configurations. The common-mode voltage of the clock inputs is set to VCM using internal 5-kΩ resistors as shown in Figure 97.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 1000 Impedance (Magnitude) − Ω 900 800 700 600 500 400 300 200 100 0 0 25 50 75 100 125 Clock Frequency − MHz G082 Figure 98. Clock Buffer Input Impedance 0.1 mF CLKP Differential Sine-Wave or PECL or LVDS Clock Input 0.1 mF CLKM ADS612x Figure 99. Differential Clock Driving Circuit 0.1 mF CMOS Clock Input CLKP 0.1 mF CLKM ADS612x Figure 100.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 POWER DOWN MODES ADS612X has four power-down modes – global power down, standby, output buffer disable and input clock stopped. These modes can be set using the serial interface or using the parallel interface (pins SDATA and PDN). Table 16.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 DIGITAL OUTPUT INTERFACE ADS612X outputs 12 data bits together with an output clock. The output interface are either parallel CMOS or DDR LVDS voltage levels and can be selected using serial register bit or parallel pin SEN. Parallel CMOS Interface In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V (typical).
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 Pins OVR CLKOUT D0 D1 CMOS Output Buffers D2 D3 D4 D5 D6 12 bit ADC data D7 D8 D9 D10 D11 ADS612X Figure 101.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 DDR LVDS Interface The LVDS interface works only with 3.3 V DRVDD supply. In this mode, the 12 data bits and the output clock are available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits are multiplexed and output on each LVDS differential pair every clock cycle (DDR - Double Data Rate, see Figure 102 ).
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 CLKOUTM CLKOUTP D0_D1_P, D0_D1_M D0 D1 D0 D1 D2_D3_P, D2_D3_M D2 D3 D2 D3 D4_D5_P, D4_D5_M D4 D5 D4 D5 D6_D7_P, D6_D7_M D6 D7 D6 D7 D8_D9_P, D8_D9_M D8 D9 D8 D9 D10_D11_P, D10_D11_M D10 D11 D10 D11 Sample N Sample N+1 Figure 103.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 Figure 104. LVDS Eye Diagram - No Internal Termination 5-pF Load Capacitance Blue Trace - Output Clock (CLKOUT) Pink Trace - Output Data Figure 105. LVDS Eye Diagram with 100-Ω Internal Termination 10-pF Load Capacitance Blue Trace - Output Clock (CLKOUT) Pink Trace - Output Data Output Data Format Two output data formats are supported – 2s complement and offset binary.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give good performance, provided the analog, digital and clock sections of the board are cleanly partitioned. See the EVM User Guide (SLWU028) for details on layout and grounding. Supply Decoupling As ADS612X already includes internal decoupling, minimal external decoupling can be used without loss in performance.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 Signal-to-Noise Ratio SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first nine harmonics.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 AC Power Supply Rejection Ratio (AC PSRR) AC PSRR is the measure of rejection of variations in the supply voltage of the ADC.
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ADS6125, ADS6124 ADS6123, ADS6122 www.ti.com SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 REVISION HISTORY Changes from Original (October 2007) to Revision A .................................................................................................... Page • • • Changed DDR LVDS output data sequence in Figure 1 ..................................................................................................... 11 Changed pin configuration (CMOS mode) information..................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS6122IRHBR VQFN RHB 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS6122IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS6123IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS6122IRHBR VQFN RHB 32 3000 338.1 338.1 20.6 ADS6122IRHBT VQFN RHB 32 250 210.0 185.0 35.0 ADS6123IRHBR VQFN RHB 32 3000 338.1 338.1 20.6 ADS6123IRHBT VQFN RHB 32 250 210.0 185.0 35.0 ADS6124IRHBR VQFN RHB 32 3000 338.1 338.1 20.6 ADS6124IRHBT VQFN RHB 32 250 210.0 185.0 35.
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