Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal VQFN 48

FEATURES

APPLICATIONS

DESCRIPTION

ADS6245 , ADS6244

ADS6243 , ADS6242

SLAS542A – MAY 2007 – REVISED JULY 2007

www.ti.com

DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

• Pin Compatible 12-Bit Family (ADS622X -

SLAS543A )

• Maximum Sample Rate: 125 MSPS

• Feature Compatible Quad Channel Family

• 14-Bit Resolution with No Missing Codes

(ADS644X - SLAS531A and ADS642X -

• Simultaneous Sample and Hold

SLAS532A )

• 3.5 dB Coarse Gain and up to 6 dB

Programmable Fine Gain for SFDR/SNR

Trade-Off

• Base-Station IF Receivers

• Serialized LVDS Outputs with Programmable

• Diversity Receivers

Internal Termination Option

• Medical Imaging

• Supports Sine, LVCMOS, LVPECL, LVDS

• Test Equipment

Clock Inputs and Amplitude down to 400 mV

• Internal Reference with External Reference

Table 1. ADS62XX Dual Channel Family

Support

125 MSPS 105 MSPS 80 MSPS 65 MSPS

• No External Decoupling Required for

ADS624X

ADS6245 ADS6244 ADS6243 ADS6242

References

14 Bit

ADS622X

• 3.3-V Analog and Digital Supply

ADS6225 ADS6224 ADS6223 ADS6222

12 Bit

• 48 QFN Package (7 mm × 7 mm)

Table 2. Performance Summary

ADS6245 ADS6244 ADS6243 ADS6242

Fin = 10MHz (0 dB gain) 87 91 92 93

SFDR, dBc

Fin = 170MHz (3.5 dB gain) 79 83 84 84

Fin = 10MHz (0 dB gain) 73.4 73.4 74.2 74.3

SINAD, dBFS

Fin = 170MHz (3.5 dB gain) 68.3 69.3 69.4 70

Power, per channel, mW 500 405 350 315

ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS

dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a

compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes

3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In

addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it

possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing

receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling

frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit

clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and

bit clocks are also transmitted as LVDS outputs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (76 pages)

PAGE 1
ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS • FEATURES 1 • • • • • • • • • • Maximum Sample Rate: 125 MSPS 14-Bit Resolution with No Missing Codes Simultaneous Sample and Hold 3.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD Analog supply voltage 3.0 3.3 3.6 V LVDD 3.0 3.3 3.6 V SUPPLIES LVDS Buffer supply voltage ANALOG INPUTS Differential input voltage range 2 Vpp 1.5 ±0.1 Input common-mode voltage Voltage applied on VCM in external reference mode 1.45 1.50 V 1.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 DIGITAL CHARACTERISTICS The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = LVDD = 3.3V, IO = 3.5mA, RLOAD = 100Ω (1). All LVDS specifications are characterized, but not tested at production. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 2.4 V Low-level input voltage 0.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TIMING SPECIFICATIONS (1) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TIMING SPECIFICATIONS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF , IO = 3.5 mA, RL = 100 Ω , no internal termination, unless otherwise noted.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Sample N+13 Sample N+12 Sample N+11 Sample N Input Signal tA Input Clock CLKM CLKP tPD_CLK Latency 12 Clocks DCLKP Bit Clock DCLKM Output Data DOM DOP D13 D12 D11 D10 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 Sample N–1 Frame Clock D6 D5 D4 D3 D2 D1 D0 Sample N FCLKM FCLKP T0105-04 Figure 1. Latency DCLKP Bit Clock DCLKM tsu th tsu Output Data DOP, DOM th Dn+1 Dn T0106-03 Figure 2.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 DEVICE PROGRAMMING MODES ADS624X offers flexibility with several programmable features that are easily configured. The device can be configured independently using either parallel interface control or serial interface programming. In addition, the device supports a third configuration mode, where both the parallel interface and the serial control registers are used.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Table 4. Priority Between Parallel Pins and Serial Registers PIN CFG1 to CFG4 FUNCTIONS SUPPORTED PRIORITY As described in Register bits can control the modes ONLY if the bit is high. If the bit is LOW, then the control voltage on these parallel pins determines the function as per Tables PDNA Channel A power down D2 bit of register 0x00 controls channel A power down ONLY if PDNA pin is LOW.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Independent of the programming mode used, after power-up the parallel pins PDNA, PDNB, CFG1 to CFG4 will automatically configure the device as per the voltage applied (Table 7 to Table 12). Table 7. PDNA Control Pin PDNA DESCRIPTION 0 Normal operation AVDD Channel A ADC Power down Table 8. PDNB Control Pin PDNB DESCRIPTION 0 Normal operation AVDD Channel B ADC Power down Table 9.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 SERIAL INTERFACE The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, unless otherwise noted.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 SERIAL REGISTER MAP Table 13.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 DESCRIPTION OF SERIAL REGISTERS Table 14.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Table 15. Serial Register B REGISTER ADDRESS A4 - A0 04 BITS D10 D9 0 D8 0 0 D7 D6 D5 D4 D3 D2 INPUT CLOCK BUFFER GAIN CONTROL 0 D6 - D2 Input clock buffer gain control 11000 Gain 0 Minimum gain 00000 Gain 1, default after reset 01100 Gain 2 01010 Gain 3 01001 Gain 4 01000 Gain 5 Maximum gain D1 D0 0 0 Table 16.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Table 17. Serial Register D REGISTER ADDRESS A4 - A0 BITS D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 CUSTOM PATTERN (LOWER 11 BITS) 0B D10 - D0 Lower 11 bits of custom pattern … Table 18.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 D5 Coarse gain control 0 0 dB coarse gain 1 3.5dB coarse gain (Full-scale range = 1.34 Vpp) D6 MSB or LSB first selection 0 MSB First 1 LSB First D7 Byte/bit wise outputs (only when 2-wire is selected) 0 Byte wise 1 Bit wise D10 Over-ride bit. All the functions in register 0x0D can also be controlled using the parallel control pins.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 D10-D6 LVDS internal termination for bit and word clock outputs 00000 No internal termination 00001 166 Ω 00010 200 Ω 00100 250 Ω 01000 333 Ω 10000 500 Ω Any combination of above bits can also be programmed, resulting in a parallel combination of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω 100 Ω 00101 Table 21.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued) PINS NAME NO. SCLK 34 SDATA 33 SEN 32 I/O I I I NO. OF PINS DESCRIPTION 1 This pin functions as serial interface clock input when RESET is low. When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with SDATA). See Table 5 for description. This pin has an internal pull-down resistor.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued) PINS I/O NO. OF PINS 34 I 1 This pin functions as serial interface clock input when RESET is low. When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with SDATA). See Table 5 for description. This pin has an internal pull-down resistor. 33 I 1 This pin functions as serial interface data input when RESET is low.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS - ADS6245 (Fs = 125 MSPS) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless otherwise noted) FFT for 10 MHz INPUT SIGNAL FFT for 100 MHz INPUT SIGNAL 0 0 SFDR = 88 dBc SINAD = 74 dBFS SNR = 74.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS - ADS6245 (Fs = 125 MSPS) (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS - ADS6245 (Fs = 125 MSPS) (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless otherwise noted) PERFORMANCE vs CLOCK AMPLITUDE 86 PERFORMANCE vs CLOCK DUTY CYCLE 90 77 78 fIN = 50.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS - ADS6244 (Fs = 105 MSPS) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless otherwise noted) FFT for 10 MHz INPUT SIGNAL FFT for 100 MHz INPUT SIGNAL 0 SFDR = 91.2 dBc SINAD = 73.9 dBFS SNR = 74.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS - ADS6244 (Fs = 105 MSPS) (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS - ADS6244 (Fs = 105 MSPS) (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless otherwise noted) PERFORMANCE vs CLOCK AMPLITUDE 92 PERFORMANCE vs CLOCK DUTY CYCLE 93 76 fIN = 70.1 MHz 90 76 fIN = 20.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS - ADS6243 (Fs = 80 MSPS) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless otherwise noted) FFT for 10 MHz INPUT SIGNAL FFT for 100 MHz INPUT SIGNAL 0 SFDR = 91 dBc SINAD = 74.2 dBFS SNR = 74.4 dBFS THD = 88.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS - ADS6243 (Fs = 80 MSPS) (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS - ADS6243 (Fs = 80 MSPS) (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless otherwise noted) PERFORMANCE vs CLOCK AMPLITUDE 92 fIN = 50.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS - ADS6242 (Fs = 65 MSPS) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless otherwise noted) FFT for 10 MHz INPUT SIGNAL FFT for 100 MHz INPUT SIGNAL 0 SFDR = 92.4 dBc SINAD = 74.3 dBFS SNR = 74.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS - ADS6242 (Fs = 65 MSPS) (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS - ADS6242 (Fs = 65 MSPS) (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless otherwise noted) PERFORMANCE vs CLOCK AMPLITUDE 96 PERFORMANCE vs CLOCK DUTY CYCLE 95 80 fIN = 50.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Contour Plots across Input and Sampling Frequencies 125 120 92 89 80 86 83 fS - Sampling Frequency - MSPS 110 65 86 80 83 89 74 100 77 83 90 86 80 86 83 80 70 68 71 74 86 89 80 60 68 71 77 65 83 50 89 86 30 10 83 50 74 80 150 100 68 71 77 40 200 250 300 65 400 350 450 500 fIN - Input Frequency - MHz 65 75 70 80 85 90 SFDR - dBc M0049-13 Figure 78.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Contour Plots across Input and Sampling Frequencies (continued) 125 120 68 fS - Sampling Frequency - MSPS 73 74 110 64 67 72 70 71 65 66 69 100 90 66 68 80 70 72 73 74 71 64 65 67 69 70 60 66 64 65 50 67 40 74 30 10 50 69 71 70 72 73 150 100 68 66 200 250 64 65 300 63 400 350 62 450 500 fIN - Input Frequency - MHz 60 70 65 75 SNR - dBFS M0048-13 Figure 80.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 APPLICATION INFORMATION THEORY OF OPERATION The ADS6245/ADS6244/ADS6243 (ADS624X) is a family of dual channel, 14-bit pipeline ADC based on switched capacitor architecture in CMOS technology. The conversion is initiated simultaneously by all the four channels at the rising edge of the external input clock.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 1 Magnitude − dB 0 −1 −2 −3 −4 −5 −6 0 100 200 300 400 500 fIN − Input Frequency − MHz 600 700 G073 Figure 83. Analog Input Bandwidth (represented by magnitude of TF_ADC, see Figure 85 ) Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 F1 Freq = 50 MHz S(1, 1) = 0.967 / –13.241 Impedance = 62.211 – j421.739 1000 F1 Frequency = 50 MHz Mag(Zin1) = 426.302 900 700 F2 Frequency = 400 MHz Mag(Zin1) = 65.193 600 F1 500 S(1, 1) Magnitude of Zin -- W 800 400 F2 300 200 F1 F2 100 0 0 50 100 150 200 250 300 350 400 450 500 fI -- Input Frequency -- MHz Frequency (100 kHz to 500 MHz) F2 Freq = 400 MHz S(1, 1) = 0.273 / –59.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 TF_ADC 0.1 mF ADS6xxx 5W INP 0.1 mF 25 W 25 W INM 5W 1:1 VCM S0256-01 Figure 85. Single Transformer Drive Circuit At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Using Differential Amplifier Drive Circuits Figure 87 shows a drive ciruit using a differential amplifier (TI's THS4509) to convert a single-ended input to differential output that can be interfaced to the ADC input pins. In addition to the single-ended to differential conversion, the amplifier also provides gain (10dB in Figure 87).
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 INTREF Internal Reference VCM 1 kW INTREF 4 kW EXTREF REFM REFP ADS6xxx S0165-04 Figure 88. Reference Section Internal Reference When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog input pins.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the SFDR improvement is significant with marginal degradation in SINAD. The gains can be programmed using the register bits (Table 19) and (Table 18).
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Clock Buffer Lpkg » 3 nH 10 W CLKP Cbond » 1 pF Ceq Ceq 5 kW Resr » 100 W VCM 6 pF 5 kW Lpkg » 3 nH 10 W CLKM Cbond » 1 pF Resr » 100 W Ceq » 1 to 3 pF, equivalent input capacitance of clock buffer S0275-01 Figure 89. Internal Clock Buffer 1000 Impedance (Magnitude) − Ω 900 800 700 600 500 400 300 200 100 0 0 25 50 75 100 125 Clock Frequency − MHz G082 Figure 90.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 0.1 mF CLKP Differential Sine-Wave or PECL or LVDS Clock Input 0.1 mF CLKM ADS6xxx S0167-05 Figure 91. Differential Clock Driving Circuit Figure 92 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance with this scheme is comparable with that of a low jitter sine wave clock source.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Table 24. Power Down Modes Summary (1) (1) POWER DOWN MODE AVDD POWER (mW) LVDD POWER (mW) WAKE UP TIME In power-up 782 208 – Global power down 65 12 100 μs 1 Channel in standby 510 208 200 Clocks 2 Channels in standby 235 208 200 Clocks Input clock stop 200 35 100 μs Sampling frequency = 125 MSPS. POWER SUPPLY SEQUENCING During power-up, the AVDD and LVDD supplies can come up in any sequence.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 DIGITAL OUTPUT INTERFACE The ADS624X offers several flexible output options making it easy to interface to an ASIC or an FPGA. Each of these options can be easily programmed using either parallel pins or the serial interface.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 2-WIRE INTERFACE - 14× SERIALIZATION The 14-bit ADC data is serialized and output over two LVDS pairs. A frame clock at 1× sample frequency is also available with an SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5× sample frequency. The output data rate will be 7 × Sample frequency as 7 data bits are output every clock cycle on each wire.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Input Clock, CLK Freq = Fs Frame Clock, FCLK Freq = 0.5 ´ Fs In Byte-Wise Mode Bit Clock – DDR, DCLK Freq = 3.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 OUTPUT BIT ORDER In the 2-wire interface, three types of bit order are supported - byte-wise, bit-wise and word-wise. Byte-wise: Each 14-bit sample is split across the 2 wires. Wires DA0 and DB0 carry the 7 LSB bits D6-D0 and wires DA1 and DB1 carry the 7 MSB bits. Bit-wise: Each 14-bit sample is split across the 2 wires. Wires DA0 and DB0 carry the 7 even bits (D0,D2,D4..
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 C001 Figure 98. LVDS Data Eye Diagram with 5-pF Load Capacitance (No Internal Termination) C002 Figure 99.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 CAPTURE TEST PATTERNS ADS624X outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is recommended to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB. This ensures sufficient setup/hold times for a reliable capture by the receiver. The DESKEW is a 1010... or 0101...
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES Setup, hold and other timing parameters are specified across sampling frequencies and for each type of output interface in the tables below. Table 29 to Table 32: Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, CL = 5 pF, IO = 3.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Table 30. Timings for 2-Wire Interface, DDR Bit Clock SERIALIZATION DATA SETUP TIME, tsu ns SAMPLING FREQUENCY MSPS 14× 16× DATA HOLD TIME, th ns MIN TYP MIN TYP 105 0.45 0.65 MAX 0.5 0.7 92 0.55 0.75 0.6 0.8 80 0.65 0.85 0.7 0.9 65 0.8 1.1 0.8 1.1 40 1.4 1.7 1.5 1.9 105 0.35 0.55 0.4 0.6 92 0.45 0.65 0.5 0.7 80 0.55 0.75 0.6 0.8 65 0.6 0.9 0.7 1 40 1.1 1.4 1.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give optimum performance, provided the analog, digital and clock sections of the board are cleanly partitioned. Refer to the EVM User Guide (SLAU196) for more layout details. Supply Decoupling As the ADS624X already includes internal decoupling, minimal external decoupling can be used without loss in performance.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
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ADS6245, ADS6244 ADS6243, ADS6242 www.ti.com SLAS542A – MAY 2007 – REVISED JULY 2007 Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS6242IRGZR VQFN RGZ 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS6242IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS6243IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS6242IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS6242IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 ADS6243IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS6243IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 ADS6244IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS6244IRGZT VQFN RGZ 48 250 336.6 336.6 28.
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