Datasheet

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DEVICE PROGRAMMING MODES
USING PARALLEL INTERFACE CONTROL ONLY
USING SERIAL INTERFACE PROGRAMMING ONLY
USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS
ADS6245 , ADS6244
ADS6243 , ADS6242
SLAS542A – MAY 2007 – REVISED JULY 2007
ADS624X offers flexibility with several programmable features that are easily configured.
The device can be configured independently using either parallel interface control or serial interface
programming.
In addition, the device supports a third configuration mode, where both the parallel interface and the serial control
registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority
table (Table 4 ). If this additional level of flexibility is not required, the user can select either the serial interface
programming or the parallel interface control.
To control the device using parallel interface, keep RESET tied to high (LVDD). Pins CFG1, CFG2, CFG3,
CFG4, PDNA, PDNB, SEN, SCLK, and SDATA are used to directly control certain functions of the ADC. After
power-up, the device will automatically get configured as per the parallel pin voltage settings (Table 5 to Table 9 )
and no reset is required. In this mode, SEN, SCLK, and SDATA function as parallel interface control pins.
Frequently used functions are controlled in this mode — output data interface and format, power down modes,
coarse gain and internal/external reference. The parallel pins can be configured using a simple resistor string as
illustrated in Figure 3 .
Table 3 has a description of the modes controlled by the parallel pins.
Table 3. Parallel Pin Definition
PIN CONTROL FUNCTIONS
SEN Coarse gain and internal/external reference.
SCLK, SDATA Sync, deskew patterns and global power down.
PDNA, PDNB Dedicated pins for individual channel power down
CFG1 1-wire/2-wire and DDR/SDR bit clock
CFG2 14x/16x serialization and SDR bit clock capture edge
CFG3 Reserved function. Tie CFG3 to Ground.
CFG4 MSB/LSB First and data format.
In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal
registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET
pin or by a high setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low.
The serial interface section describes the register programming and register reset in more detail.
Since the parallel pins (CFG1-4, PDNA and PDNB) are not used in this mode, they must be tied to ground. The
register override bit <OVRD> - D10 in register 0x0D has to be set high to disable the control of parallel interface
pins in this serial interface control ONLY mode.
For increased flexibility, a combination of serial interface registers and parallel pin controls (CFG1-4, PDNA and
PDNB) can also be used to configure the device.
The parallel interface control pins CFG1 to CFG4 and PDNA, PDNB are available. After power-up, the device will
automatically get configured as per the parallel pin voltage settings (Table 5 to Table 12 ) and no reset is
required. A simple resistor string can be used as illustrated in Figure 3 .
SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.
The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high
setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low.
The serial interface section describes the register programming and register reset in more detail.
Since some functions are controlled using both the parallel pins and serial registers, the priority between the two
is determined by a priority table (Table 4 ).
12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242