Datasheet

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(3/8) AVDD
(3/8) AVDD
ToParallelPin
3R
AVDD
AVDDGND
GND
3R
2R
(5/8) AVDD
(5/8) AVDD
DESCRIPTION OF PARALLEL PINS
ADS6245 , ADS6244
ADS6243 , ADS6242
SLAS542A – MAY 2007 – REVISED JULY 2007
Table 4. Priority Between Parallel Pins and Serial Registers
PIN FUNCTIONS SUPPORTED PRIORITY
CFG1 to Register bits can control the modes ONLY if the <OVRD> bit is high. If the <OVRD> bit is
As described in
CFG4 LOW, then the control voltage on these parallel pins determines the function as per Tables
D2 bit of register 0x00 controls channel A power down ONLY if PDNA pin is LOW. If PDNA is
PDNA Channel A power down
high, channel A is powered down.
D3 bit of register 0x00 controls channel B power down ONLY if PDNB pin is LOW. If PDNB is
PDNB Channel B power down
high, channel B is powered down.
COARSE GAIN setting is controlled by bit D5 of register 0X0D ONLY if the <OVRD> bit is high.
Else, it is in default register setting of 0 dB COARSE GAIN.
SEN Serial Interface Enable
INTERNAL/ EXTERNAL Reference setting is determined by bit D6 of register 0x00.
D7, D6, D5 bits of register 0x0A control the SYNC and DESKEW output patterns.
SCLK, Serial Interface Clock and
SDATA Serial Interface Data pins
Power down is determined by bit D0 of 0x00 register.
Figure 3. Simple Scheme to Configure Parallel Pins
Table 5. SCLK, SDATA Control Pins
SCLK SDATA DESCRIPTION
LOW LOW NORMAL conversion.
SYNC - ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the
LOW HIGH
deserialized data to the frame boundary. See Capture Test Patterns for details.
POWER DOWN – Global power down, all channels of the ADC are powered down, including internal references,
HIGH LOW
PLL and output buffers.
DESKEW - ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure
HIGH HIGH
deserializer uses the right clock edge. See Capture Test Patterns for details.
Table 6. SEN Control Pin
SEN DESCRIPTION
0 External reference and 0 dB coarse gain (Full-scale = 2V pp)
(3/8)LVDD External reference and 3.5 dB coarse gain (Full-scale = 1.34V pp)
(5/8)LVDD Internal reference and 3.5 dB coarse gain (Full-scale = 1.34V pp)
LVDD Internal reference and 0 dB coarse gain (Full-scale = 2V pp)
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