Datasheet

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ADS6245 , ADS6244

ADS6243 , ADS6242

SLAS542A – MAY 2007 – REVISED JULY 2007

Independent of the programming mode used, after power-up the parallel pins PDNA, PDNB, CFG1 to CFG4 will

automatically configure the device as per the voltage applied (Table 7 to Table 12 ).

Table 7. PDNA Control Pin

PDNA DESCRIPTION

0 Normal operation

AVDD Channel A ADC Power down

Table 8. PDNB Control Pin

PDNB DESCRIPTION

0 Normal operation

AVDD Channel B ADC Power down

Table 9. CFG1 Control Pin

CFG1 DESCRIPTION

0 DDR bit clock and 1-wire interface

(3/8)LVDD Not used

(5/8)LVDD SDR bit clock and 2-wire interface

LVDD DDR bit clock and 2-wire interface

Table 10. CFG2 Control Pin

CFG2 DESCRIPTION

0 14x serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock

mode)

(3/8)LVDD 16x serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock

mode)

(5/8)LVDD 16x serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock

mode)

LVDD 14x serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock

mode)

Table 11. CFG3 Control Pin

CFG3 RESERVED - TIE TO GROUND

Table 12. CFG4 Control Pin

CFG4 DESCRIPTION

0 MSB First and 2s complement

(3/8)LVDD MSB First and Offset binary

(5/8)LVDD LSB First and Offset binary

LVDD LSB First and 2s complement

Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242