Datasheet

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ADS6245 , ADS6244
ADS6243 , ADS6242
SLAS542A – MAY 2007 – REVISED JULY 2007
Table 17. Serial Register D
REGISTER
BITS
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
<CUSTOM A>
0B
CUSTOM PATTERN (LOWER 11 BITS)
D10 - D0 <CUSTOM A> Lower 11 bits of custom pattern <DATAOUT10> … <DATAOUT0>
Table 18. Serial Register E
REGISTER
BITS
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
<FINE GAIN> <CUSTOM B>
0C 0 0 0
FINE GAIN CONTROL (1 dB to 6 dB) CUSTOM PATTERN (UPPER 5 BITS)
D4 - D0 <CUSTOM B> Upper 5 bits of custom pattern <DATAOUT15> … <DATAOUT11>
D10-D8 <FINE GAIN> Fine gain control
000 0 dB gain (Full-scale range = 2.00 Vpp)
001 1 dB gain (Full-scale range = 1.78 Vpp)
010 2 dB gain (Full-scale range = 1.59 Vpp)
011 3 dB gain (Full-scale range = 1.42 Vpp)
100 4 dB gain (Full-scale range = 1.26 Vpp)
101 5 dB gain (Full-scale range = 1.12 Vpp)
110 6 dB gain (Full-scale range = 1.00 Vpp)
Table 19. Serial Register F
REGISTER
BITS
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
<COARSE FALLING OR
<OVRD> BYTE-WISE GAIN> RISING BIT 14-BIT OR DDR OR 1-WIRE OR
MSB OR
0D OVER-RIDE 0 0 OR COURSE CLOCK 0 16-BIT SDR BIT 2-WIRE
LSB FIRST
BITE BIT-WISE GAIN CAPTURE SERIALIZE CLOCK INTERFACE
ENABLE EDGE
D0 Interface selection
0 1 wire interface
1 2 wire interface
D1 Bit clock selection (only in 2-wire interface)
0 DDR bit clock
1 SDR bit clock
D2 Serialization factor selection
0 14X serialization
1 16X serialization
D4 Bit clock capture edge (only when SDR bit clock is selected, D1=1)
0 Capture data with falling edge of bit clock
1 Capture data with rising edge of bit clock
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