Datasheet

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PIN CONFIGURATION (2-WIRE INTERFACE)
P0023-05
ADS624x
RGZPACKAGE
(TOP VIEW)
LGND
AVDD
LVDD
NC
CAP
CFG4
RESET
CM
LVDD
AGND
AGND
CLKP
AVDD
CLKM
AGND
AGND
AGND
CFG3
INA_M
CFG2
INA_P
CFG1
AGND
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17
18 19 20 21 22 23 24
LVDD
DA0_M
LGND
DA0_P
SCLK
DA1_M
SDATA
DA1_P
SEN
DCLK_M
PDNA
DCLK_P
PDNB
FCLK_M
AGND
FCLK_P
AGND
DB0_M
INB_M
DB0_P
INB_P
DB1_M
AGND
DB1_P
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45
44 43 42 41 40 39 38 37
PAD
ADS6245 , ADS6244
ADS6243 , ADS6242
SLAS542A – MAY 2007 – REVISED JULY 2007
PIN ASSIGNMENTS (2-WIRE INTERFACE)
PINS NO.
I/O OF DESCRIPTION
NAME NO.
PINS
SUPPLY AND GROUND PINS
AVDD 7,13,24 3 Analog power supply
6,8,9,12,17,
AGND 9 Analog ground
20,25,28,29
LVDD 2,5,36 3 Digital power supply
LGND 1,35 2 Digital ground
INPUT PINS
CLKP, CLKM 18,19 I 2 Differential input clock pair
Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not
INA_P, INA_M 11,10 I 2
float.
Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not
INB_P, INB_M 26,27 I 2
float.
CAP 3 I 1 Connect 2nF capacitor from pin to ground
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242