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SNR − dBFS
70
71
72
73
74
75
76
77
72
74
76
78
80
82
84
86
0.5 1.0 1.5 2.0 2.5 3.0
SFDR − dBc
Input Clock Amplitude − V
PP
G013
SNR
SFDR
f
IN
= 50.1 MHz
SNR − dBFS
72
73
74
75
76
77
78
Input Clock Duty Cycle − %
84
85
86
87
88
89
90
35 40 45 50 55 60 65
SFDR − dBc
G014
SNR
SFDR
f
IN
= 20.1 MHz
f
S
− Sampling Frequency − MSPS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 25 50 75 100 125
P
D
− Power Dissipation − W
G015
LVDD
AVDD
Output Code
0
5
10
15
20
25
30
35
40
8187 8188 8189 8190 8191 8192 8193 8194 8195 8196
Occurence − %
G016
RMS (LSB) = 1.064
f − Frequency − MHz
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 50 100 150 200 250 300
CMRR − Common-Mode Rejection Ratio − dBc
G018
SNR − dBFS
68
70
72
74
76
78
V
VCM
− VCM Voltage − V
84
86
88
90
92
94
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
f
IN
= 50.1 MHz
External Reference Mode
SFDR − dBc
G017
SNR
SFDR
ADS6245 , ADS6244
ADS6243 , ADS6242
SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6245 (F
s
= 125 MSPS) (continued)
All plots are at 25 ° C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V
PP
differential
clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs CLOCK DUTY CYCLE
Figure 18. Figure 19.
OUTPUT NOISE HISTOGRAM WITH
POWER DISSIPATION vs SAMPLING FREQUENCY INPUTS TIED TO COMMON-MODE
Figure 20. Figure 21.
PERFORMANCE IN EXTERNAL REFERENCE MODE CMRR vs FREQUENCY
Figure 22. Figure 23.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 29
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