Datasheet

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S0167-05
CLKP
CLKM
DifferentialSine-Wave
orPECL orLVDSClockInput
ADS6xxx
0.1 Fm
0.1 Fm
V
CC
V
CC
REF_IN
VCXO_INM
CP_OUT
CTRL
OUTP
OUTM
Y0B
Y0
ADS6xxx
CLKM
CLKP
VCXO
CDCM7005
VCXO_INP
Reference Clock
S0238-02
S0168-07
CLKP
CLKM
CMOSClockInput
ADS6xxx
0.1 Fm
0.1 Fm
ADS6245 , ADS6244
ADS6243 , ADS6242
SLAS542A – MAY 2007 – REVISED JULY 2007
Figure 91. Differential Clock Driving Circuit
Figure 92 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance
with this scheme is comparable with that of a low jitter sine wave clock source.
Figure 92. PECL Clock Drive Using CDCM7005
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin) connected to ground with a
0.1- μ F capacitor, as shown in Figure 93 .
Figure 93. Single-Ended Clock Driving Circuit
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 49
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242