Datasheet

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CLOCK BUFFER GAIN

POWER DOWN MODES

Global Power Down

Channel Standby

Input Clock Stop

ADS6245 , ADS6244

ADS6243 , ADS6242

SLAS542A – MAY 2007 – REVISED JULY 2007

For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode

noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass

filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a

non-50% duty cycle clock input.

When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is

increased. Hence, it is recommended to use large clock amplitude. Use clock amplitude greater than 1V pp to

avoid performance degradation.

In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock

amplitude. The gain can be set by programming the register bits <CLKIN GAIN> (Table 15 ) and increases

monotonically from Gain 0 to Gain 4 settings. Table 23 shows the minimum clock amplitude supported for each

gain setting.

Table 23. Minimum Clock Amplitude across gains

MINIMUM CLOCK AMPLITUDE SUPPORTED, mV pp

CLOCK BUFFER GAIN

differential

Gain 0 (Minimum gain) 800

Gain 1 (default gain) 400

Gain 2 300

Gain 3 200

Gain 4 (Highest gain) 150

The ADS624X has three power down modes – global power down, channel standby and input clock stop.

This is a global power down mode in which almost the entire chip is powered down, including the four ADCs,

internal references, PLL and LVDS buffers. As a result, the total power dissipation falls to about 77 mW typical

(with input clock running). This mode can be initiated by setting the register bit <PDN GLOBAL> (Table 14 ). The

output data and clock buffers are in high impedance state.

The wake-up time from this mode to data becoming valid in normal mode is 100 μ s.

In this mode, only the ADC of each channel is powered down and this helps to get very fast wake-up times. Each

of the four ADCs can be powered down independently using the register bits <PDN CH> (Table 14 ). The output

LVDS buffers remain powered up.

The wake-up time from this mode to data becoming valid in normal mode is 200 clock cycles.

The converter enters this mode:

• If the input clock frequency falls below 1 MSPS or

• If the input clock amplitude is less than 400 mV (pp, differential with default clock buffer gain setting) at any

sampling frequency.

All ADCs and LVDS buffers are powered down and the power dissipation is about 235 mW. The wake-up time

from this mode to data becoming valid in normal mode is 100 μ s.

Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242