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D13
(D0)
0
(D0)
D1
(0)
0
(D0)
0
(D1)
D0
(0)
0
(D1)
D13
(D2)
D12
(D3)
D11
(D4)
D10
(D5)
D9
(D6)
D7
(D8)
D8
(D7)
D6
(D9)
D5
(D10)
D4
(D11)
D3
(D12)
D2
(D13)
D13
(D2)
D6
(D7)
D10
(D3)
D3
(D10)
D7
(D6)
D0
(D13)
D12
(D1)
D12
(D1)
D5
(D8)
D9
(D4)
D2
(D11)
D11
(D2)
D4
(D9)
D8
(D5)
D1
(D12)
D13
(D0)
DataBitinLSBFirstMode
DataBitinMSBFirstMode
(1)
In16-Bitserialization,twozerobitsarepaddedtothe14-bit ADCdataontheMSBside.
OutputData
DA,DB,DC,DD
DataRate=16 Fs´
16-BitSerialization
(1)
InputClock,
CLKP/M
Freq=Fs
FrameClock,
FCLKP
Freq=1 Fs´
BitClock – DDR,
DCLKP/M
Freq=8 Fs´
T0225-02
OutputData
DA,DB,DC,DD
DataRate=14 Fs´
12-BitSerialization
BitClock – DDR,
DCLKP/M
Freq=7 Fs´
SampleN SampleN+1
2-WIRE INTERFACE – 16 × SERIALIZATION WITH DDR/SDR BIT CLOCK
ADS6245 , ADS6244
ADS6243 , ADS6242
SLAS542A – MAY 2007 – REVISED JULY 2007
Figure 94. 1-Wire Interface
The 2-wire interface is recommended for sampling frequencies above 65 MSPS. In 16 × serialization, two zero
bits are padded to the 14-bit ADC data on the MSB side and the combined 16-bit data is serialized and output
over two LVDS pairs. The data rate is 8 × Sample frequency since 8 bits are sent on each wire every clock cycle.
The data is available along with DDR bit clock or optionally with SDR bit clock. Each ADC sample is sent over
the 2 wires as byte-wise or bit-wise or word-wise.
Using the 16 × serialization makes it possible to upgrade to a 16-bit ADC in the future seamlessly, without
requiring any modification to the receiver capture logic design.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 53
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