Datasheet

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OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
ADS6245 , ADS6244
ADS6243 , ADS6242
SLAS542A – MAY 2007 – REVISED JULY 2007
Setup, hold and other timing parameters are specified across sampling frequencies and for each type of output
interface in the tables below.
Table 29 to Table 32 : Typical values are at 25 ° C, min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD = LVDD = 3.3 V, C
L
= 5 pF, I
O
= 3.5 mA, R
L
= 100 Ω , no internal termination,
unless otherwise noted.
Timing parameters are ensured by design and characterization and not tested in production.
Ts = 1/ Sampling frequency = 1/Fs
Table 28. Clock Propagation Delay for different interface options
CLOCK PROPAGATION DELAY, SERIALIZER LATENCY
(1)
INTERFACE SERIALIZATION
t
pd_clk
clock cycles
14x t
pd_clk
= 0.428xT
s
+ t
delay
1-wire with DDR bit clock 0
16x t
pd_clk
= 0.375xT
s
+ t
delay
2
(when t
pd_clk
≥ T
s
)
2-wire with DDR bit clock t
pd_clk
= 0.857xT
s
+ t
delay
14x 1
(when t
pd_clk
< T
s
)
2-wire with SDR bit clock t
pd_clk
= 0.428xT
s
+ t
delay
0
1
(when t
pd_clk
≥ T
s
)
2-wire with DDR bit clock t
pd_clk
= 0.75xT
s
+ t
delay
16x 0
(when t
pd_clk
< T
s
)
2-wire with SDR bit clock t
pd_clk
= 0.375xT
s
+ t
delay
0
(1) Note that the total latency = ADC latency + internal serializer latency. The ADC latency is 12 clock cycles.
Table 29. Timings for 1-Wire Interface
DATA SETUP TIME, t
su
DATA HOLD TIME, t
h
t
delay
SAMPLING
ns ns ns
SERIALIZATION FREQUENCY
MSPS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 0.3 0.5 0.4 0.6 F
s
≥ 40 MSPS
40 0.65 0.85 0.7 0.9 3 4 5
14 ×
20 1.3 1.65 1.6 1.9 F
s
< 40 MSPS
10 3.2 3.5 3.2 3.6 3 4.5 6
F
s
≥ 40 MSPS
3 4 5
16 × 65 0.22 0.42 0.35 0.55
F
s
< 40 MSPS
3 4.5 6
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