Datasheet

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ADS6245 , ADS6244
ADS6243 , ADS6242
SLAS542A – MAY 2007 – REVISED JULY 2007
Table 30. Timings for 2-Wire Interface, DDR Bit Clock
DATA SETUP TIME, t
su
DATA HOLD TIME, t
h
t
delay
SAMPLING
ns ns ns
SERIALIZATION FREQUENCY
MSPS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
105 0.45 0.65 0.5 0.7 F
s
≥ 45 MSPS
92 0.55 0.75 0.6 0.8
3.4 4.4 5.4
14 × 80 0.65 0.85 0.7 0.9
65 0.8 1.1 0.8 1.1 F
s
< 45 MSPS
40 1.4 1.7 1.5 1.9 3.7 5.2 6.7
105 0.35 0.55 0.4 0.6 F
s
≥ 45 MSPS
92 0.45 0.65 0.5 0.7
3.4 4.4 5.4
16 × 80 0.55 0.75 0.6 0.8
65 0.6 0.9 0.7 1 F
s
< 45 MSPS
40 1.1 1.4 1.3 1.7 3.7 5.2 6.7
Table 31. Timings for 2-Wire Interface, SDR Bit Clock
DATA SETUP TIME, t
su
DATA HOLD TIME, t
h
t
delay
SAMPLING
ns ns ns
SERIALIZATION FREQUENCY
MSPS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 0.8 1 1 1.2 F
s
≥ 40 MSPS
40 1.5 1.7 1.6 1.8 3.4 4.4 5.4
14 ×
20 3.4 3.6 3.3 3.5 F
s
< 40 MSPS
10 6.9 7.2 6.6 6.9 3.7 5.2 6.7
65 0.65 0.85 0.8 1.0 F
s
≥ 40 MSPS
40 1.3 1.5 1.4 1.6 3.4 4.4 5.4
16 ×
20 2.8 3.0 2.8 3.0 F
s
< 40 MSPS
10 6.0 6.3 5.8 6.1 3.7 5.2 6.7
Table 32. Output Jitter (applies to all interface options)
BIT CLOCK JITTER, CYCLE-CYCLE FRAME CLOCK JITTER, CYCLE-CYCLE
SAMPLING FREQUENCY
ps, peak-peak ps, peak-peak
MSPS
MIN TYP MAX MIN TYP MAX
≥ 65 350 75
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