Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal VQFN 64

FEATURES APPLICATIONS

DESCRIPTION

ADS6424

ADS6423

ADS6422

www.ti.com

............................................................................................................................................. SLAS532A – MAY 2007 – REVISED JUNE 2007

QUAD CHANNEL, 12-BIT, 105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE

• Base-station IF Receivers

• 12-Bit Resolution With No Missing Codes

• Diversity Receivers

• Simultaneous Sample and Hold

• Medical Imaging

• 3.5dB Coarse Gain and upto 6dB

• Test Equipment

Programmable Fine Gain for SFDR/SNR

Trade-Off

Table 1. ADS64XX Quad Channel Family

• Serialized LVDS Outputs With Programmable

125 MSPS 105 MSPS 80 MSPS 65 MSPS

Internal Termination Option

ADS644X

• Supports Sine, LVCMOS, LVPECL, LVDS

ADS6445 ADS6444 ADS6443 ADS6442

14 Bit

Clock Inputs and Amplitude down to 400

ADS642X ADS6425

ADS6424 ADS6423 ADS6422

12 Bit (SLWS197 )

• Internal Reference With External Reference

Support

• No External Decoupling Required for

References

• 3.3-V Analog and Digital Supply

• 64 QFN Package (9 mm × 9 mm)

• Pin Compatible 14-Bit Family (ADS644X -

SLAS531A )

• Feature Compatible Dual Channel Family

(ADS624X - SLAS542 A, ADS622X - SLAS543 A)

Table 2. Performance Summary

ADS6425 ADS6424 ADS6423 ADS6422

Fin = 10MHz (0 dB gain) 90 91 91 93

SFDR, dBc

Fin = 170MHz (3.5 dB gain) 79 81 82 83

Fin = 10MHz (0 dB gain) 70.7 71.1 71.3 71.3

SINAD, dBFS

Fin = 170MHz (3.5 dB gain) 67.4 68.1 68.2 68.7

Power per channel, mW 420 340 300 265

The ADS6424/ADS6423/ADS6422 (ADS642X) is a family of high performance 12-bit 105/80/65 MSPS quad

channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact

64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB

coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to

the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it

possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing

receiver design. The ADS642X also includes the traditional 1-wire interface that can be used at lower sampling

frequencies.

Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data

sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (71 pages)

PAGE 1
ADS6424 ADS6423 ADS6422 www.ti.com ............................................................................................................................................. SLAS532A – MAY 2007 – REVISED JUNE 2007 QUAD CHANNEL, 12-BIT, 105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE FEATURES APPLICATIONS • • • • • • • 1 • • • • • • • • 12-Bit Resolution With No Missing Codes Simultaneous Sample and Hold 3.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 12-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD Analog supply voltage 3.0 3.3 3.6 V LVDD 3.0 3.3 3.6 V SUPPLIES LVDS Buffer supply voltage ANALOG INPUTS Differential input voltage range 2 Vpp 1.5 ±0.1 Input common-mode voltage Voltage applied on VCM in external reference mode 1.45 1.50 V 1.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 TIMING SPECIFICATIONS (1) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 TIMING SPECIFICATIONS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF , IO = 3.5 mA, RL = 100 Ω , no internal termination, unless otherwise noted.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 DCLKP Bit Clock DCLKM tsu th tsu Output Data DOP, DOM th Dn+1 Dn T0106-03 Figure 2.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 DEVICE PROGRAMMING MODES ADS642X offers flexibility with several programmable features that are easily configured. The device can be configured independently using either parallel interface control or serial interface programming. In addition, the device supports a third configuration mode, where both the parallel interface and the serial control registers are used.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 Table 4. Priority Between Parallel Pins and Serial Registers PIN FUNCTIONS SUPPORTED PRIORITY As described in Table 8 to Table 11 Register bits can control the modes only if the register bit is high. If is low, then the control voltage on these parallel pins determines the function. PDN Global Power Down Register bit controls global power down only if PDN pin is low.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 DESCRIPTION OF PARALLEL PINS Table 5. SCLK, SDATA Control Pins SCLK SDATA LOW LOW NORMAL conversion. DESCRIPTION LOW HIGH SYNC - ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the deserialized data to the frame boundary. See Capture Test Patterns for details.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 SERIAL INTERFACE The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, unless otherwise noted.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 SERIAL REGISTER MAP Table 12.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 DESCRIPTION OF SERIAL REGISTERS Table 13.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 Table 14. Serial Register B REGISTER ADDRESS A4 - A0 04 BITS D10 0 D9 0 D8 D7 0 D6 D5 D4 D3 D2 INPUT CLOCK BUFFER GAIN CONTROL 0 D6 - D2 Input clock buffer gain control 11000 Gain 0, minimum gain 00000 Gain 1, default gain after reset 01100 Gain 2 01010 Gain 3 01001 Gain 4 01000 Gain 5, maximum gain D1 D0 0 0 Table 15.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 Table 16. Serial Register D REGISTER ADDRESS A4 - A0 BITS D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 CUSTOM PATTERN (LOWER 11 BITS) 0B D10 - D0 Lower 11 bits of custom pattern … Table 17.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 D4 Bit clock capture edge (only when SDR bit clock is selected, D1 = 1) 0 Capture data with falling edge of bit clock 1 Capture data with rising edge of bit clock D5 Coarse gain control 0 0 dB coarse gain 1 3.5dB coarse gain (full-scale range = 1.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 D10-D6 LVDS internal termination for bit and word clock outputs 00000 No internal termination 00001 166 Ω 00010 200 Ω 00100 250 Ω 01000 333 Ω 10000 500 Ω Any combination of above bits can also be programmed, resulting in a parallel combination of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω 100 Ω 00101 Table 20.
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ADS6424 ADS6423 ADS6422 www.ti.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued) PINS NAME NO. I/O NO. OF PINS DESCRIPTION INB_P, INB_M 15,14 I 2 Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not float. INC_P, INC_M 34,35 I 2 Differential input signal pair, channel C. If unused, the pins should be tied to VCM. Do not float. IND_P, IND_M 37,38 I 2 Differential input signal pair, channel D.
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ADS6424 ADS6423 ADS6422 www.ti.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued) PINS NAME IND_P, IND_M NO. 37,38 I/O NO. OF PINS I 2 Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do not float. 1 Connect 2-nF capacitance from pin to ground DESCRIPTION CAP 5 SCLK 44 I 1 This pin functions as serial interface clock input when RESET is low.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless otherwise noted) ADS6424 (Fsrated = 105 MSPS) FFT for 10 MHz INPUT SIGNAL FFT for 100 MHz INPUT SIGNAL 0 SFDR = 91.7 dBc SINAD = 71.2 dBFS SNR = 71.2 dBFS THD = 89.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ADS6424 (Fsrated = 105 MSPS) (continued) SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS 92 72 Input adjusted to get −1dBFS input 90 4 dB 88 2 dB 70 3 dB 84 82 6 dB 80 69 68 67 2 dB 66 78 4 dB 1 dB 0 dB 76 65 74 64 10 30 50 70 90 110 130 150 170 190 210 230 fIN − Input Frequency − MHz 5 dB 6 dB 20 40 60 80 G007 PERFORMANCE vs AVDD PERFORMANCE vs LVDD fIN = 70.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ADS6424 (Fsrated = 105 MSPS) (continued) PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs CLOCK DUTY CYCLE 74 90 82 74 fIN = 20.1 MHz 73 fIN = 70.1 MHz 80 71 84 70 82 69 80 78 72 76 68 SFDR 78 1.0 1.5 2.0 74 66 3.0 2.5 Input Clock Amplitude − VPP 70 72 69 35 40 45 50 55 60 65 Input Clock Duty Cycle − % G013 G014 Figure 18. Figure 19.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ADS6423 (Fsrated = 80 MSPS) FFT for 10 MHz INPUT SIGNAL FFT for 100 MHz INPUT SIGNAL 0 −20 −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 f − Frequency − MHz 40 0 10 20 G019 40 G020 Figure 24. Figure 25. FFT for 230 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 SFDR = 81 dBc SINAD = 68.3 dBFS SNR = 68.4 dBFS THD = 79.5 dBc −20 fIN1 = 185.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ADS6423 (Fsrated = 80 MSPS) (continued) SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS 94 74 Input adjusted to get −1dBFS input 92 72 5 dB 88 86 3 dB 84 82 6 dB 2 dB 71 SINAD − dBFS 90 SFDR − dBc 73 4 dB 3.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ADS6423 (Fsrated = 80 MSPS) (continued) PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs CLOCK DUTY CYCLE 75 88 73 SFDR 86 SFDR 72 84 71 SNR 82 70 80 69 78 68 73 80 72 78 76 71 SNR 74 76 0.5 fIN = 50.1 MHz 1.0 1.5 2.0 67 3.0 2.5 70 72 35 40 45 50 G032 Figure 37. POWER DISSIPATION vs SAMPLING FREQUENCY OUTPUT NOISE HISTOGRAM WITH INPUTS TIED TO COMMON-MODE 40 1.8 35 RMS (LSB) = 0.407 1.6 30 1.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ADS6422 (Fsrated = 65 MSPS) FFT for 10 MHz INPUT SIGNAL FFT for 100 MHz INPUT SIGNAL 0 −20 −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 f − Frequency − MHz 0 10 30 G037 G038 Figure 42. Figure 43. FFT for 230 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 SFDR = 81.5 dBc SINAD = 68.1 dBFS SNR = 68.4 dBFS THD = 80.3 dBc −20 fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ADS6422 (Fsrated = 65 MSPS) (continued) SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS 96 74 Input adjusted to get −1dBFS input 94 92 3 dB 4 dB 88 86 84 6 dB 82 3.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 ADS6422 (Fsrated = 65 MSPS) (continued) PERFORMANCE vs CLOCK AMPLITUDE 96 PERFORMANCE vs CLOCK DUTY CYCLE 78 fIN = 50.1 MHz 94 83 74 fIN = 20.1 MHz 77 81 88 74 86 73 84 SFDR 79 82 72 77 72 SNR 71 SNR 75 70 71 80 0.5 1.0 1.5 70 2.5 2.0 Input Clock Amplitude − VPP 73 69 35 40 45 50 60 65 Input Clock Duty Cycle − % G049 G050 Figure 55.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 Contour Plots Across Input and Sampling Frequencies 105 fS - Sampling Frequency - MSPS 100 90 84 87 90 69 81 66 84 75 81 80 72 78 69 84 84 70 63 75 87 90 66 72 78 60 84 84 50 69 78 93 40 87 75 84 96 72 66 84 30 10 50 150 100 200 250 300 400 350 450 500 fIN - Input Frequency - MHz 60 70 65 75 90 85 80 95 SFDR - dBc M0049-10 Figure 60.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 Contour Plots Across Input and Sampling Frequencies (continued) 105 100 69 70 71 64 65 fS - Sampling Frequency - MSPS 66 90 67 68 80 70 70 71 65 69 64 66 60 67 68 50 71 66 68 30 10 50 100 200 63 64 67 150 64 65 69 70 40 250 300 62 400 350 450 500 fIN - Input Frequency - MHz 60 66 64 62 68 70 72 SNR - dBFS M0048-10 Figure 62.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 APPLICATION INFORMATION THEORY OF OPERATION The ADS6425/ADS6424/ADS6423/ADS6422 (ADS642X) is a family of quad channel, 12-bit pipeline ADC up to 125 MSPS sampling frequency. The conversion is initiated simultaneously by all the four channels at the rising edge of the external input clock.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) 1 Magnitude − dB 0 −1 −2 −3 −4 −5 −6 0 100 200 300 400 500 fIN − Input Frequency − MHz 600 700 G073 Figure 65. Analog Input Bandwidth (represented by magnitude of TF_ADC, see Figure 67 ) Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) F1 Freq = 50 MHz S(1, 1) = 0.967 / –13.241 Impedance = 62.211 – j421.739 1000 F1 Frequency = 50 MHz Mag(Zin1) = 426.302 900 700 F2 Frequency = 400 MHz Mag(Zin1) = 65.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) TF_ADC 0.1 mF ADS6xxx 5W INP 0.1 mF 25 W 25 W INM 5W 1:1 VCM S0256-01 Figure 67. Single Transformer Drive Circuit At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) Using Differential Amplifier Drive Circuits Figure 69 shows a drive ciruit using a differential amplifier (TI's THS4509) to convert a single-ended input to differential output that can be interfaced to the ADC input pins. In addition to the single-ended to differential conversion, the amplifier also provides gain (10dB in Figure 69).
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) REFERENCE The ADS642X has built-in internal references REFP and REFM, requiring no external components. Design schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the requisite reference capacitors eliminates the need for external decoupling.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) COARSE GAIN AND PROGRAMMABLE FINE GAIN ADS642X includes gain settings that can be used to get improved SFDR performance (compared to 0 dB gain mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each gain setting, the analog input full-scale range scales proportionally, as listed in Table 21. The coarse gain is a fixed setting of 3.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 VCM VCM 5 kW 5 kW CLKP CLKM ADS6xxx S0166-04 Figure 71. Internal Clock Buffer 0.1 mF CLKP Differential Sine-Wave or PECL or LVDS Clock Input 0.1 mF CLKM ADS6xxx S0167-05 Figure 72. Differential Clock Driving Circuit Figure 73 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance with this scheme is comparable with that of a low jitter sine wave clock source.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 VCC Reference Clock REF_IN VCC Y0 CLKP Y0B CLKM CDCM7005 VCXO_INP OUTM VCXO_INM CP_OUT ADS6xxx VCXO OUTP CTRL S0238-02 Figure 73. PECL Clock Drive Using CDCM7005 Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin) connected to ground with a 0.1-μF capacitor, as shown in Figure 74. 0.1 mF CMOS Clock Input CLKP 0.1 mF CLKM ADS6xxx S0168-07 Figure 74.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 Table 22. Minimum Clock Amplitude Across Gains CLOCK BUFFER GAIN MINIMUM CLOCK AMPLITUDE SUPPORTED, mVPP differential Gain 0 (minimum gain) 800 Gain 1 (default gain) 400 Gain 2 300 Gain 3 200 Gain 4 (highest gain) 150 POWER DOWN MODES The ADS642X has three power down modes – global power down, channel standby and input clock stop.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 DIGITAL OUTPUT INTERFACE The ADS642X offers several flexible output options making it easy to interface to an ASIC or an FPGA. Each of these options can be easily programmed using either parallel pins or the serial interface.
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ADS6424 ADS6423 ADS6422 www.ti.
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ADS6424 ADS6423 ADS6422 www.ti.
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ADS6424 ADS6423 ADS6422 SLAS532A – MAY 2007 – REVISED JUNE 2007 www.ti.com 2-WIRE INTERFACE - 14× SERIALIZATION In 14× serialization, two zero bits are padded to the 14-bit ADC data on the MSB side and the combined 14-bit data is serialized and output over two LVDS pairs. A frame clock at 1× sample frequency is also available with an SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5× sample frequency.
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ADS6424 ADS6423 ADS6422 www.ti.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 Input Clock, CLK Freq = Fs Frame Clock, FCLK Freq = 0.5 ´ Fs In Byte-Wise Mode Bit Clock – DDR, DCLK Freq = 3.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 OUTPUT BIT ORDER In the 2-wire interface, three types of bit order are supported - byte-wise, bit-wise and word-wise. Byte-wise: Each 14-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 6 LSB bits D5-D0 and wires DA1, DB1, DC1 and DD1 carry the 6 MSB bits. Bit-wise: Each 14-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 6 even bits (D0,D2,D4..
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 C001 Figure 79. LVDS Data Eye Diagram with 5-pF Load Capacitance (No Internal Termination) C002 Figure 80.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 CAPTURE TEST PATTERNS ADS642X outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is recommended to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB. This ensures sufficient setup/hold times for a reliable capture by the receiver. The DESKEW is a 1010... or 0101...
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES Setup, hold and other timing parameters are specified across sampling frequencies and for each type of output interface in the following tables. Table 28 to Table 31: Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, CL = 5 pF , IO = 3.5 mA, RL = 100 Ω , no internal termination, unless otherwise noted.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 Table 30. Timings for 2-Wire Interface, SDR Bit Clock SERIALIZATION DATA SETUP TIME, tsu ns DATA HOLD TIME, th ns SAMPLING FREQUENCY MSPS MIN TYP MIN TYP 65 1.0 1.2 1.1 1.3 40 1.8 2.0 1.9 2.1 20 3.9 4.1 3.8 4.1 10 8.2 8.4 7.8 8.2 65 0.8 1.0 1.0 1.2 40 1.5 1.7 1.6 1.8 20 3.4 3.6 3.3 3.5 10 6.9 7.2 6.6 6.9 12× 14× MAX tdelay ns MAX MIN TYP MAX Fs ≥ 40 MSPS 3.4 4.4 5.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay will be different across channels.
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ADS6424 ADS6423 ADS6422 www.ti.com SLAS532A – MAY 2007 – REVISED JUNE 2007 Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). P THD + 10Log10 S PD (6) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Feb-2010 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS6422IRGCR VQFN RGC 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS6422IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS6423IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS6422IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS6422IRGCT VQFN RGC 64 250 336.6 336.6 28.6 ADS6423IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS6423IRGCT VQFN RGC 64 250 336.6 336.6 28.6 ADS6424IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS6424IRGCT VQFN RGC 64 250 336.6 336.6 28.
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