ADS64XX EVM User's Guide User's Guide April 2007 SLAU196
SLAU196 – April 2007 Submit Documentation Feedback
Contents 1 Overview .................................................................................................................... 5 1.1 2 3 Circuit Description ...................................................................................................... 7 2.1 Schematic Diagram .............................................................................................. 7 2.2 ADC Circuit Function .........................................................................................
List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ................................................................................................................................. 8 ................................................................................................................................. 8 ADS64XX EVM Setup ..................................................................................................... 12 Layer 1, Top Silkscreen ...................................................
User's Guide SLAU196 – April 2007 1 Overview This user's guide gives a general overview of the evaluation module (EVM) and provides a general description of the features and functions to be considered while using this module. This manual is applicable to the ADS6445, ADS6444, ADS6443, ADS6425, ADS6424, and ADS6423, which collectively are referred to as ADS64XX.
www.ti.com Overview ADS64XX EVM. 6. ADS64XX and TSW1200: Switch power supplies on. 7. ADS64XX: Using a low-phase-noise, filtered frequency generator with 50-Ω source output impedance, generate a 0-V offset, 1.5-Vrms sine-wave clock into J12. The frequency of the clock must be within the specification for the device speed grade. TI uses an Agilent 8644B with a crystal MCF filter as a clock source. 8. TSW1200: Depress SW4 (FPGA reset).
www.ti.com Circuit Description 2 Circuit Description 2.1 Schematic Diagram The schematic diagram for the EVM is in Section 4.3. 2.2 ADC Circuit Function The following sections describe the function of individual circuits. Refer to the relevant data sheet for device operating characteristics. 2.2.1 ADC Operational Mode By default, the ADC is configured to operate in parallel-mode operation, because the surface-mount jumper asserts a 3.3-V state to the ADC reset pin.
www.ti.com Circuit Description For an ac-coupled system, users should use the voltage divider R9 and R18 to set the common-mode input of the amplifier, which should be set to the midpoint of the amplifier supply. C46 and C47 ac-couple the system, and the ADC inputs can then be biased by the R14 and R15 combination. Another ac-coupled approach, not supported on this EVM, would be to use a transformer at the outputs of the THS4509.
www.ti.com Circuit Description 2.2.4 ADC Clock Input Users should connect a filtered, low-phase-noise clock input to J12. A transformer, T5, provides the conversion from a single-ended clock signal into a differential clock signal. When selecting the clock signal level, users should account for the transformer having an impedance ratio of 4, with a voltage step-up of 2. 2.2.5 ADC Digital Outputs The ADS64XX ADC outputs serialized data, a bit clock (DCLK), and a frame clock (FCLK).
www.ti.com ADC Evaluation 3 ADC Evaluation This chapter describes how to set up a typical ADC evaluation system that is similar to what TI uses to perform testing for datasheet generation. Consequently, the information in this section is generic in nature and is applicable to all high-speed, high-resolution ADC evaluations. This chapter covers signal tone analysis, which yields ADC datasheet figures of merit such as signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR). 3.
www.ti.com ADC Evaluation 3.2 Coherent Input Frequency Selection Typical ADC analysis requires users to collect the resulting time-domain data and perform a Fourier transform to analyze the data in the frequency domain. A stipulation of the Fourier transform is that the signal must be continuous-time; however, this is not practical when looking at a finite set of ADC samples, usually collected from a logic analyzer.
www.ti.com ADC Evaluation Figure 3.
www.ti.com Physical Description 4 Physical Description This chapter describes the physical characteristics and PCB layout of the EVM. 4.1 PCB Layout The EVM comprises six layers and is 62 mils thick. The EVM features a split ground plane, which can be shorted together under the ADC by using the two exposed gold-plated strips seen in Figure 8 to make a low-impedance connection between ground planes. By default, the ground planes are not connected together and should be connected at the power supply.
www.ti.com Physical Description K002 Figure 5.
www.ti.com Physical Description K003 Figure 6.
www.ti.com Physical Description K004 Figure 7.
www.ti.com Physical Description K005 Figure 8.
www.ti.com Physical Description K006 Figure 9.
www.ti.com Physical Description 4.2 Bill of Materials Table 3 is the bill of materials for the ADS64XXEVM. Table 3. ADS64XXEVM Bill of Materials Reference Quantity Not Installed Part Part Number Manufacturer C1, C5, C8, C10 4 22 µF ECS-T1CC226R Panasonic C2, C9 2 10 µF ECS-H1CC106R Panasonic C3, C6 2 1 µF ECJ-1VB1A105K Panasonic C4, C7, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33 24 0.
www.ti.com Physical Description Table 3.
1 1 1 1 1 1 1 Banana jack black P4 Banana jack red P3 R2 750 D2 GREEN PWR_IN2 R1 750 D1 GREEN PWR_IN1 Banana jack black P2 Banana jack red 1 1 1 2 2 1 1 2 2 1 2 1 2 + + L1 2 L2 2 C10 22uF Bead 220 ohm 1 C5 22uF Bead 220 ohm 1 1 2 1 2 + + C8 22uF C1 22uF 1 2 1 2 + + C9 10uF C2 10uF 1 2 1 2 C6 1uF C3 1uF +3.3VD 1 +3.3VA 2 1 2 C7 .1uF C4 .
FPGA_RST 1 .1uF C13 +3.3VD CFG1 .1uF C14 100 R39 SW1 TP6 2 .1uF C15 J7 3 2 1 C16 .1uF 8 6 4 2 R72 1K R32 1K R73 1K RESET 1 C17 .1uF .1uF C18 +3.3VA AMP_VCM 2 2000pF C11 CAP .1uF C19 1/8W 5% .1uF TP2 +3.3VA .1uF C21 +3.3VD INB_M INB_P CM DA1_P DA1_M DA0_P DA0_M INA_M INA_P C20 R84 ZERO SERIAL INTERFACE R41 10K R33 10K PARALLEL INTERFACE +3.
S MA END J13 S MA SMA END J14 S MA SMA SIGNAL_INB 1 SIGNAL_INC 1 1 1 2 1 2 2 .1uF C32 .1uF 2 .1uF C24 .1uF C22 C30 SIGNAL_INA 1 1SIGNAL_IND 1 EN D S MA 4 3 2 5 J11 SMA 4 3 2 5 EN D J10 4 3 2 5 SLAU196 – April 2007 Submit Documentation Feedback 4 3 2 5 1:1 3 4 WBC1-1TLB 2 1 5 6 T8 1:1 3 4 WBC1-1TLB 2 1 5 6 T6 1:1 3 WBC1-1TLB 2 4 1 5 6 T3 1:1 3 4 WBC1-1TLB 2 1 5 6 T1 49.9 R70 49.9 R67 49.9 R64 49.9 R61 49.9 R57 49.9 R53 49.
J2 AMP EN D AMP_VCM 1 .1uF 16V C48 C39 .1uF 16V R18 499 PD VOUT+ VOUTCM2 C36 .1uF 16V C44 .22uF R21 49.9 C41 .1uF 16V C40 10uF 10V 348 R22 69.8 NC VINVIN+ CM1 PAD 100 1 2 11 4 17 R17 AMP_VCM 100 R12 THS4509 U2 R16 69.8 R13 R9 499 12 3 10 9 C34 10uF 10V C43 .1uF 16V C42 10uF 10V PD C37 10uF 10V +5V_AMP C38 .1uF 16V 2 1 2 348 R8 5 6 7 8 S MA 4 3 2 5 C35 .1uF 16V 16 15 14 13 VSVSVSVSVS+ VS+ VS+ VS+ 1 2 1 2 24 1 -5V_AMP 49.9 R19 49.
SLAU196 – April 2007 Submit Documentation Feedback DD1_M DD1_P DD0_M DD0_P DC1_M DC1_P DC0_M DC0_P FCLK_M FCLK_P DCLK_M DCLK_P DB1_M DB1_P DB0_M DB0_P DA1_M DA1_P DA0_M DA0_P G1 G3 G5 G7 G2 G4 G6 G8 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 J15 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 2 4 6 8
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