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Table Of Contents

FEATURES APPLICATIONS

DESCRIPTION

ADS6425

www.ti.com

......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009

QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE

• Base-Station IF Receivers

• Maximum Sample Rate: 125 MSPS

• Diversity Receivers

• 12-Bit Resolution with No Missing Codes

• Medical Imaging

• 1.65-W Total Power

• Test Equipment

• Simultaneous Sample and Hold

• 70.3 dBFS SNR at Fin = 50 MHz

• 83 dBc SFDR at Fin = 50 MHz, 0 dB Gain

The ADS6425 is a high performance 12-bit,

• 79 dBc SFDR at Fin = 170 MHz, 3.5 dB Gain

125-MSPS quad channel ADC. Serial LVDS data

• 3.5 dB Coarse Gain and up to 6 dB

outputs reduce the number of interface lines, resulting

Programmable Fine Gain for SFDR/SNR

in a compact 64-pin QFN package (9 mm × 9 mm)

that allows for high system integration density. The

Trade-Off

device includes a 3.5 dB coarse gain option that can

• Serialized LVDS Outputs with Programmable

be used to improve SFDR performance with little

Internal Termination Option

degradation in SNR. In addition to the coarse gain,

• Supports Sine, LVCMOS, LVPECL, LVDS Clock

fine gain options also exist, programmable in 1dB

Inputs and Amplitude Down to 400 mV

steps up to 6dB.

Differential

The output interface is 2-wire, where each ADC's

• Internal Reference with External Reference

data is serialized and output over two LVDS pairs.

Support

This makes it possible to halve the serial data rate

(compared to a 1-wire interface) and restrict it to less

• No External Decoupling Required for

than 1Gbps easing receiver design. The ADS6425

References

also includes the traditional 1-wire interface that can

• 3.3-V Analog and Digital Supply

be used at lower sampling frequencies.

• 64 QFN Package (9 mm × 9 mm)

An internal phase locked loop (PLL) multiplies the

• Pin Compatible 14-Bit Family (ADS644X -

incoming ADC sampling clock to derive the bit clock.

SLAS532 )

The bit clock is used to serialize the 12-bit data from

each channel. In addition to the serial data streams,

the frame and bit clocks are also transmitted as

LVDS outputs. The LVDS output buffers have

features such as programmable LVDS currents,

current doubling modes, and internal termination

options. These can be used to widen eye-openings

and improve signal integrity, easing capture by the

receiver.

The ADC channel outputs can be transmitted either

as MSB or LSB first and 2s complement or straight

binary.

The ADS6425 has internal references, but can also

support an external reference mode. The device is

specified over the industrial temperature range

( – 40 ° C to 85 ° C).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (59 pages)

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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE FEATURES APPLICATIONS • • • • • • • • • • • • 1 • • • • • • • Maximum Sample Rate: 125 MSPS 12-Bit Resolution with No Missing Codes 1.65-W Total Power Simultaneous Sample and Hold 70.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com LVDD LGND CAP AVDD AGND These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT AVDD Supply voltage range –0.3 to 3.9 V LVDD Supply voltage range –0.3 to 3.9 V Voltage between AGND and DGND –0.3 to 0.3 V Voltage between AVDD to LVDD –0.3 to 3.3 V Voltage applied to external pin, VCM –0.3 to 2.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, sampling rate = 125MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, sampling rate = 125MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 TIMING SPECIFICATIONS (1) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 DEVICE PROGRAMMING MODES The ADS6425 offers flexibility with several programmable features that are easily configured. The device can be configured independently using either parallel interface control or serial interface programming.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com Table 2. Priority Between Parallel Pins and Serial Registers PIN FUNCTIONS SUPPORTED CFG1 to CFG4 PRIORITY As described in Table 6 to Table 9 Register bits can control the modes ONLY if the bit is high.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 DESCRIPTION OF PARALLEL PINS Table 3. SCLK, SDATA Control Pins SCLK SDATA LOW LOW NORMAL conversion. DESCRIPTION LOW HIGH SYNC - ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the deserialized data to the frame boundary.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com Table 9.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 Register Address SDATA A4 A3 A2 A1 Register Data A0 D10 D9 D8 D7 D6 t(SCLK) D5 D4 D3 D2 D1 D0 t(DH) t(DSU) SCLK t(SLOADH) t(SLOADS) SEN RESET T0109-03 Figure 4.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, unless otherwise noted.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 SERIAL REGISTER MAP Table 10.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com DESCRIPTION OF SERIAL REGISTERS Table 11.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 Table 12. Serial Register B (1) REGISTER ADDRESS A4 - A0 04 (1) BITS D10 0 D9 0 D8 D7 0 D6 D5 D4 D3 D2 INPUT CLOCK BUFFER GAIN CONTROL 0 D1 D0 0 0 After a hardware or software reset, all register bits are cleared to 0.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com Table 14. Serial Register D (1) REGISTER ADDRESS A4 - A0 BITS D10 D9 D8 D7 D6 0B (1) D5 D4 D3 D2 D1 D0 D2 D1 D0 CUSTOM PATTERN (LOWER 11 BITS) After a hardware or software reset, all register bits are cleared to 0.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 D4 Bit clock capture edge (only when SDR bit clock is selected, D1 = 1) 0 Capture data with falling edge of bit clock 1 Capture data with rising edge of bit clock D5 Coarse gain control 0 0 dB coarse gain 1 3.5dB coarse gain (full-scale range = 1.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com 10 2.
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ADS6425 www.ti.com .........................................................................................................................................................
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued) PINS NAME NO. I/O NO. OF PINS DESCRIPTION INB_P, INB_M 15,14 I 2 Differential input signal pair, channel B. If unused, the pins should be tied to VCM and not floated. INC_P, INC_M 34,35 I 2 Differential input signal pair, channel C.
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ADS6425 www.ti.com .........................................................................................................................................................
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued) PINS NAME NO. I/O NO. OF PINS DESCRIPTION INB_P, INB_M 15,14 I 2 Differential input signal pair, channel B. If unused, the pins should be tied to VCM and not floated. INC_P, INC_M 34,35 I 2 Differential input signal pair, channel C.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 TYPICAL CHARACTERISTICS All plots are at 25°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 APPLICATION INFORMATION THEORY OF OPERATION The ADS6425 is a quad channel, 12-bit, 125-MSPS, pipeline ADC, based on switched capacitor architecture in CMOS technology. The conversion is initiated simultaneously by all the four channels at the rising edge of the external input clock.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com 1 0 Magnitude − dB −1 −2 −3 −4 −5 −6 0 100 200 300 400 500 600 fIN − Input Frequency − MHz 700 G022 Figure 30. Analog Input Bandwidth (represented by magnitude of TF_ADC, see Figure 31) Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 32 shows an example using two transformers (Coilcraft WBC1-1).
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com INTREF Internal Reference VCM 1 kW INTREF 4 kW EXTREF REFM REFP ADS6xxx S0165-04 Figure 33. Reference Section Internal Reference When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage (1.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 Table 19. Full-Scale Range Across Gains GAIN, dB TYPE 0 Default (after reset) FULL-SCALE, Vpp 2 3.5 Coarse setting (fixed) 1.34 1 1.78 2 1.59 3 1.42 Fine setting (programmable) 4 1.26 5 1.12 6 1.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com Figure 36 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance with this scheme is comparable with that of a low jitter sine wave clock source.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 Table 20.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com DIGITAL OUTPUT INTERFACE The ADS6425 offers several flexible output options making it easy to interface to an ASIC or an FPGA. These options can be easily programmed using either parallel pins and/or the serial interface.
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ADS6425 www.ti.com .........................................................................................................................................................
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 Figure 39. 2-Wire Interface 12× Serialization 2-WIRE INTERFACE - 14× SERIALIZATION In 14× serialization, two zero bits are padded to the 12-bit ADC data on the MSB side and the combined 14-bit data is serialized and output over two LVDS pairs.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 Input Clock, CLK Freq = Fs Frame Clock, FCLK Freq = 0.5 ´ Fs In Byte-Wise Mode Bit Clock – DDR, DCLK Freq = 3.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com OUTPUT BIT ORDER In the 2-wire interface, three types of bit order are supported - byte-wise, bit-wise and word-wise. Byte-wise: Each 12-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 6 LSB bits D5-D0 and wires DA1, DB1, DC1 and DD1 carry the 6 MSB bits.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 C001 Figure 42. LVDS Data Eye Diagram with 5-pF Load Capacitance (No Internal Termination) C002 Figure 43.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com Table 23. Test Patterns PATTERN DESCRIPTION All zeros Outputs logic low. All ones Outputs logic high. Toggle Outputs toggle pattern - alternates between 101010101010 and 010101010101 every clock cycle. Custom Outputs a 12-bit custom pattern.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES Setup, hold and other timing parameters are specified across sampling frequencies and for each type of output interface in the tables below.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com Table 28. Timings for 2-Wire Interface, SDR Bit Clock SERIALIZATION 12× 14× DATA SETUP TIME, tsu ns DATA HOLD TIME, th ns SAMPLING FREQUENCY MSPS MIN TYP MIN TYP 65 1.0 1.2 1.1 1.3 40 1.8 2.0 1.9 2.1 20 3.9 4.1 3.8 4.1 10 8.2 8.4 7.8 8.2 65 0.8 1.0 1.0 1.
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value.
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ADS6425 SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
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ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 Changes from Revision A (October 2007) to Revision B ............................................................................................... Page • • • • • • • • • • • • • • • • • Added Frame setup time to timing specifications ...........................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS6425IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS6425IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS6425IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS6425IRGCT VQFN RGC 64 250 336.6 336.6 28.
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