Datasheet

(3/6)LVDD
(3/6)LVDD
ToCFGxPins
3R
LVDD
LVDDGND
GND
R
2R
(5/6)LVDD
(5/6)LVDD
(3/8)LVDD
(3/8)LVDD
ToSENPin
3R
LVDD
LVDDGND
GND
3R
2R
(5/8)LVDD
(5/8)LVDD
ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com
Table 2. Priority Between Parallel Pins and Serial Registers
PIN FUNCTIONS SUPPORTED PRIORITY
CFG1 to As described in Table 6 to Register bits can control the modes ONLY if the < OVRD > bit is high. If the < OVRD > bit is
CFG4 Table 9 LOW, then the control voltage on these parallel pins determines the function as per Tables
D0 bit in register 0x00 controls global power down ONLY if PDN pin is LOW. If PDN is high,
PDN Global Power Down
device is in global power down mode.
3.5 dB coarse gain setting is controlled by bit D5 in register 0x0D ONLY if the < OVRD > bit is
high. Else, it is in default setting of 0 dB coarse gain.
SEN Serial Interface Enable
Internal/External reference setting is determined by bit D5 in register 0x00.
Bits D5-D7 in register 0x0A control the SYNC and DESKEW output patterns.
SCLK, Serial Interface Clock and
SDATA Serial Interface Data
Power down is determined by bit D0 in 0x00 register.
Figure 3. Simple Scheme to Configure Parallel Pins
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