Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- TIMING SPECIFICATIONS
- SERIAL INTERFACE TIMING CHARACTERISTICS
- RESET TIMING
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- THEORY OF OPERATION
- ANALOG INPUT
- INPUT COMMON MODE
- REFERENCE
- COARSE GAIN AND PROGRAMMABLE FINE GAIN
- CLOCK INPUT
- CLOCK BUFFER GAIN
- POWER DOWN MODES
- POWER SUPPLY SEQUENCING
- DIGITAL OUTPUT INTERFACE
- OUTPUT BIT ORDER
- MSB/LSB FIRST
- OUTPUT DATA FORMATS
- LVDS CURRENT CONTROL
- LVDS INTERNAL TERMINATION
- CAPTURE TEST PATTERNS
- OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
- DEFINITION OF SPECIFICATIONS
DESCRIPTION OF PARALLEL PINS
ADS6425
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......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009
Table 3. SCLK, SDATA Control Pins
SCLK SDATA DESCRIPTION
LOW LOW NORMAL conversion.
SYNC - ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the
LOW HIGH
deserialized data to the frame boundary. See Capture Test Patterns for details.
POWER DOWN – Global power down, all channels of the ADC are powered down, including internal references,
HIGH LOW
PLL and output buffers.
DESKEW - ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure
HIGH HIGH
deserializer uses the right clock edge. See Capture Test Patterns for details.
Table 4. SEN Control Pin
SEN DESCRIPTION
0 External reference and 0 dB coarse gain (full-scale = 2V pp)
(3/8)LVDD External reference and 3.5 dB coarse gain (full-scale = 1.34V pp)
(5/8)LVDD Internal reference and 3.5 dB coarse gain (full-scale = 1.34V pp)
LVDD Internal reference and 0 dB coarse gain (full-scale = 2V pp)
Independent of the programming mode used, after power-up the parallel pins PDN, CFG1 to CFG4 will
automatically configure the device as per the voltage applied (Table 5 to Table 9 ).
Table 5. PDN Control Pin
PDN DESCRIPTION
0 Normal operation
AVDD Power down global
Table 6. CFG1 Control Pin
CFG1 DESCRIPTION
0 (default) DDR Bit clock and 1-wire interface
+200mV
(3/6)LVDD Not used
± 200mV
(5/6)LVDD SDR Bit clock and 2-wire interface
± 200mV
LVDD DDR Bit clock and 2-wire interface
- 200mV
Table 7. CFG2 Control Pin
CFG2 DESCRIPTION
0 (default) 12x Serialization and capture at falling edge of bit clock (only with SDR bit clock)
+200mV
(3/6)LVDD 14x Serialization and capture at falling edge of bit clock (only with SDR bit clock)
± 200mV
(5/6)LVDD 14x Serialization and capture at rising edge of bit clock (only with SDR bit clock)
± 200mV
LVDD 12x Serialization and capture at rising edge of bit clock (only with SDR bit clock)
- 200mV
Table 8. CFG3 Control Pin
CFG3 RESERVED - TIE TO GROUND
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