Datasheet

SERIAL REGISTER MAP
ADS6425
www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009
Table 10. Summary of Functions Supported By Serial Interface
REGISTER
REGISTER FUNCTIONS
(1) (2) (3)
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
< PDN
< REF >
< PDN CHD > < PDN CHC > < PDN CHB > < PDN CHA > GLOBAL >
< RST > INTERNAL
00 0 0 0 0 POWER POWER POWER POWER GLOBAL
S/W RESET OR
DOWN CH D DOWN CHC DOWN CH B DOWN CH A POWER
EXTERNAL
DOWN
< CLKIN GAIN >
04 0 0 0 0 0 0
INPUT CLOCK BUFFER GAIN CONTROL
< DF >
DATA
FORMAT 2S < PATTERNS >
0A 0 0 0 0 0 0 0
COMP OR TEST PATTERNS
STRAIGHT
BINARY
< CUSTOM A >
0B
CUSTOM PATTERN (LOWER 11 BITS)
< CUSTOM
B >
< FINE GAIN >
0C 0 0 0 0 0 0 0 CUSTOM
FINE GAIN CONTROL (1dB to 6 dB)
PATTERN
(MSB BIT)
< COARSE FALLING OR
< OVRD > BYTE-WISE GAIN > RISING BIT 12-BIT OR DDR OR 1-WIRE OR
MSB OR
0D OVERRIDE 0 0 OR COURSE CLOCK 0 14-BIT SDR BIT 2-WIRE
LSB FIRST
BIT BIT-WISE GAIN CAPTURE SERIALIZE CLOCK INTERFACE
ENABLE EDGE
< TERM CLK > < LVDS CURR > < CURR DOUBLE >
10
LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS LVDS CURRENT SETTINGS LVDS CURRENT DOUBLE
< TERM DATA >
11 WORD-WISE CONTROL 0 0 0 0
LVDS INTERNAL TERMINATION - DATA OUTPUTS
(1) The unused bits in each register (shown by blank cells in above table) must be programmed as 0.
(2) Multiple functions in a register can be programmed in a single write operation.
(3) After a hardware or software reset, all register bits are cleared to 0.
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