Datasheet

ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com
Table 14. Serial Register D
(1)
REGISTER
BITS
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
< CUSTOM A >
0B
CUSTOM PATTERN (LOWER 11 BITS)
(1) After a hardware or software reset, all register bits are cleared to 0.
D10 - D0 < CUSTOM A > Lower 11 bits of custom pattern < D10 > … < D0 >
Table 15. Serial Register E
(1)
REGISTER
BITS
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
< CUSTOM
B >
< FINE GAIN >
0C 0 0 0 0 0 0 0 CUSTOM
FINE GAIN CONTROL (1 dB to 6 dB)
PATTERN
(MSB BIT)
(1) After a hardware or software reset, all register bits are cleared to 0.
D4 - D0 < CUSTOM B > MSB bit of custom pattern < D11 >
D10-D8 < FINE GAIN > Fine gain control
000 0 dB Gain (full-scale range = 2.00 V
PP
)
001 1 dB Gain (full-scale range = 1.78 V
PP
)
010 2 dB Gain (full-scale range = 1.59 V
PP
)
011 3 dB Gain (full-scale range = 1.42 V
PP
)
100 4 dB Gain (full-scale range = 1.26 V
PP
)
101 5 dB Gain (full-scale range = 1.12 V
PP
)
110 6 dB Gain (full-scale range = 1.00 V
PP
)
Table 16. Serial Register F
(1)
REGISTER
BITS
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
< COARSE FALLING OR
< OVRD > BYTE-WISE GAIN > RISING BIT 14-BIT OR DDR OR 1-WIRE OR
MSB OR
0D OVER-RIDE 0 0 OR COARSE CLOCK 0 16-BIT SDR BIT 2-WIRE
LSB FIRST
BITE BIT-WISE GAIN CAPTURE SERIALIZE CLOCK INTERFACE
ENABLE EDGE
(1) After a hardware or software reset, all register bits are cleared to 0.
D0 Interface selection
0 1 Wire interface
1 2 Wire interface
D1 Bit clock selection (only in 2-wire interface)
0 DDR Bit clock
1 SDR Bit clock
D2 Serialization selection
0 12x Serialization
1 14x Serialization
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