Datasheet

ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com
10 2.5 mA
11 3 mA
D10-D6 < TERM CLK > LVDS internal termination for bit and word clock outputs
00000 No internal termination
00001 166 Ω
00010 200 Ω
00100 250 Ω
01000 333 Ω
10000 500 Ω
Any combination of above bits can also be programmed, resulting in a parallel combination of
the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω
00101 100 Ω
Table 18. Serial Register H
(1)
REGISTER
BITS
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
< TERM DATA >
11 WORD-WISE CONTROL 0 0 0 0
LVDS INTERNAL TERMINATION - DATA OUTPUTS
(1) After a hardware or software reset, all register bits are cleared to 0.
D4-D0 < TERM DATA > LVDS internal termination for data outputs
00000 No internal termination
00001 166 Ω
00010 200 Ω
00100 250 Ω
01000 333 Ω
10000 500 Ω
Any combination of above bits can also be programmed, resulting in a parallel combination
of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω
00101 100 Ω
D10-D9 Only when 2-wire interface is selected
00 Byte-wise or bit-wise output, 1x frame clock
11 Word-wise output enabled, 0.5x frame clock
01,10 Do not use
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