Datasheet

PIN CONFIGURATION (1-WIRE INTERFACE)
ADS6425
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RGCPACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
UNUSED
UNUSED
UNUSED
UNUSED
CAP
RESET
LVDD
AGND
AVDD
AGND
INA_M
INA_P
AGND
INB_M
INB_P
AGND
AVDD
AGND
AVDD
NC
CFG4
VCM
AGND
CLKP
CLKM
AGND
A
VDD
CFG3 CFG2 CFG1
AGND
AVDD
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
UNUSED
UNUSED
UNUSED
UNUSED
SCLK
SDATA
SEN
PDN
AVDD
AGND
IND_M
IND_P
AGND
INC_M
INC_P
AGND
LVDD DA_M DA_P DB_M DB_P LGND DCLKM DCLKP FCLKM FCLKP LGND DC_M DC_P DD_M DD_P LVDD
P0056-03
ADS6425
www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009
PIN ASSIGNMENTS (1-WIRE INTERFACE)
PINS
NO. OF
I/O DESCRIPTION
PINS
NAME NO.
SUPPLY AND GROUND PINS
AVDD 9,17,19,27,32,40, 6 Analog power supply
8,10,13,16,18,23,26,
AGND 31,33 11 Analog ground
36,39,
LVDD 7,49,64 3 Digital power supply
LGND 54,59 2 Digital ground
INPUT PINS
CLKP, CLKM 24,25 I 2 Differential input clock pair
Differential input signal pair, channel A. If unused, the pins should be tied to
INA_P, INA_M 12,11 I 2
VCM and not floated.
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): ADS6425