Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- TIMING SPECIFICATIONS
- SERIAL INTERFACE TIMING CHARACTERISTICS
- RESET TIMING
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- THEORY OF OPERATION
- ANALOG INPUT
- INPUT COMMON MODE
- REFERENCE
- COARSE GAIN AND PROGRAMMABLE FINE GAIN
- CLOCK INPUT
- CLOCK BUFFER GAIN
- POWER DOWN MODES
- POWER SUPPLY SEQUENCING
- DIGITAL OUTPUT INTERFACE
- OUTPUT BIT ORDER
- MSB/LSB FIRST
- OUTPUT DATA FORMATS
- LVDS CURRENT CONTROL
- LVDS INTERNAL TERMINATION
- CAPTURE TEST PATTERNS
- OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
- DEFINITION OF SPECIFICATIONS
ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 .........................................................................................................................................................
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PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued)
PINS
NO. OF
I/O DESCRIPTION
PINS
NAME NO.
Differential input signal pair, channel B. If unused, the pins should be tied to
INB_P, INB_M 15,14 I 2
VCM and not floated.
Differential input signal pair, channel C. If unused, the pins should be tied to
INC_P, INC_M 34,35 I 2
VCM and not floated.
Differential input signal pair, channel D. If unused, the pins should be tied to
IND_P, IND_M 37,38 I 2
VCM and not floated.
CAP 5 1 Connect 2nF capacitance from pin to ground
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN
SCLK 44 I 1
modes (along with SDATA). See Table 3 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN
SDATA 43 I 1
modes (along with SCLK). See Table 3 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference
SEN 42 I 1
modes. See Table 4 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin or by using
RESET 6 I 1 software reset option. Refer to the Serial Interface section. In parallel interface
mode, tie RESET permanently high. (SCLK, SDATA and SEN function as
parallel control pins in this mode).
The pin has an internal pull-down resistor to ground.
PDN 41 I 1 Global power down control pin.
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock
CFG1 30 I 1 selection. See Table 6 for description.
Tie to ground for 1-wire interface with DDR bit clock.
Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture
CFG2 29 I 1 edge. See Table 7 for description.
For 12x serialization with DDR bit clock, tie to ground or AVDD.
CFG3 28 I 1 RESERVED pin - Tie to ground.
Parallel input pin. It controls data format and MSB or LSB first modes. See
CFG4 21 I 1
Table 9 for description.
Internal reference mode – common-mode voltage output
VCM 22 I/O 1 External reference mode – reference input. The voltage forced on this pin sets
the internal reference.
OUTPUT PINS
DA_P,DA_M 62,63 O 2 Channel A differential LVDS data output pair
DB_P,DB_M 60,61 O 2 Channel B differential LVDS data output pair
DC_P,DC_M 52,53 O 2 Channel C differential LVDS data output pair
DD_P,DD_M 50,51 O 2 Channel D differential LVDS data output pair
DCLKP,DCLKM 57,58 O 2 Differential bit clock output pair
FCLKP,FCLKM 55,56 O 2 Differential frame clock output pair
UNUSED 1-4,45-48 8 These pins are unused in the 1-wire interface. Do not connect
NC 20 1 Do not connect
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