Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- TIMING SPECIFICATIONS
- SERIAL INTERFACE TIMING CHARACTERISTICS
- RESET TIMING
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- THEORY OF OPERATION
- ANALOG INPUT
- INPUT COMMON MODE
- REFERENCE
- COARSE GAIN AND PROGRAMMABLE FINE GAIN
- CLOCK INPUT
- CLOCK BUFFER GAIN
- POWER DOWN MODES
- POWER SUPPLY SEQUENCING
- DIGITAL OUTPUT INTERFACE
- OUTPUT BIT ORDER
- MSB/LSB FIRST
- OUTPUT DATA FORMATS
- LVDS CURRENT CONTROL
- LVDS INTERNAL TERMINATION
- CAPTURE TEST PATTERNS
- OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
- DEFINITION OF SPECIFICATIONS

LV
DD
− Supply Voltage − V
78
82
86
90
94
98
3.0 3.1 3.2 3.3 3.4 3.5 3.6
SFDR − dBc
G012
SNR − dBFS
68
69
70
71
72
73
f
IN
= 50.1 MHz
AV
DD
= 3.3 V
SNR
SFDR
T − Temperature − °C
74
76
78
80
82
84
86
−40 −20 0 20 40 60 80
SFDR − dBc
G013
SNR − dBFS
68
69
70
71
72
73
74
f
IN
= 50.1 MHz
SNR
SFDR
Input Amplitude − dBFS
30
40
50
60
70
80
90
100
110
−60 −50 −40 −30 −20 −10 0
f
IN
= 20 MHz
SFDR − dBc, dBFS
G014
SNR − dBFS
68
69
70
71
72
73
74
75
76
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
Input Clock Amplitude − V
PP
76
78
80
82
84
86
88
90
92
0.5 1.0 1.5 2.0 2.5 3.0
SFDR − dBc
G015
SNR − dBFS
66
67
68
69
70
71
72
73
74
SNR
SFDR
f
IN
= 50.1 MHz
f
S
− Sampling Frequency − MSPS
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 25 50 75 100 125
P
D
− Power Dissipation − W
G016
LVDD
AVDD
Input Clock Duty Cycle − %
84
85
86
87
88
89
90
35 40 45 50 55 60 65
SFDR − dBc
G020
SNR − dBFS
65
67
69
71
73
75
77
SNR
SFDR
f
IN
= 20.1 MHz
ADS6425
www.ti.com
......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009
TYPICAL CHARACTERISTICS (continued)
All plots are at 25 ° C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 V
PP
differential
clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain, 32K point FFT
(unless otherwise noted)
PERFORMANCE vs LVDD PERFORMANCE vs TEMPERATURE
Figure 18. Figure 19.
PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE
Figure 20. Figure 21.
PERFORMANCE vs CLOCK DUTY CYCLE POWER DISSIPATION vs SAMPLING FREQUENCY
Figure 22. Figure 23.
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