Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- TIMING SPECIFICATIONS
- SERIAL INTERFACE TIMING CHARACTERISTICS
- RESET TIMING
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- THEORY OF OPERATION
- ANALOG INPUT
- INPUT COMMON MODE
- REFERENCE
- COARSE GAIN AND PROGRAMMABLE FINE GAIN
- CLOCK INPUT
- CLOCK BUFFER GAIN
- POWER DOWN MODES
- POWER SUPPLY SEQUENCING
- DIGITAL OUTPUT INTERFACE
- OUTPUT BIT ORDER
- MSB/LSB FIRST
- OUTPUT DATA FORMATS
- LVDS CURRENT CONTROL
- LVDS INTERNAL TERMINATION
- CAPTURE TEST PATTERNS
- OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
- DEFINITION OF SPECIFICATIONS
2010 40 60
80
f -InputFrequency-MHz
IN
f -SamplingFrequency-MSPS
S
SFDR-dBc
100 120 140
180
200 220160 230
40
50
100
60
70
80
90
110
120
125
76
74
78
80
88868482 90 92 94 95
M0049-12
83
86
86
83
83
80
77
83
86
86
89
89
89
92
92
ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 .........................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
All plots are at 25 ° C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 V
PP
differential
clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain, 32K point FFT
(unless otherwise noted)
Figure 28. SFDR Contour
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