Datasheet

CLOCK INPUT
S0166-04
CLKP
VCM
5kW
5kW
CLKM
VCM
ADS6xxx
S0167-05
CLKP
CLKM
DifferentialSine-Wave
orPECL orLVDSClockInput
ADS6xxx
0.1 Fm
0.1 Fm
ADS6425
www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009
Table 19. Full-Scale Range Across Gains
GAIN, dB TYPE FULL-SCALE, V
pp
0 Default (after reset) 2
3.5 Coarse setting (fixed) 1.34
1 1.78
2 1.59
3 1.42
Fine setting
(programmable)
4 1.26
5 1.12
6 1.00
The ADS6425 clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5-k Ω resistors as shown in Figure 34 . This allows using transformer-coupled drive circuits for
sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure 35 and Figure 37 ).
Figure 34. Internal Clock Buffer
Figure 35. Differential Clock Driving Circuit
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Product Folder Link(s): ADS6425