Datasheet

V
CC
V
CC
REF_IN
VCXO_INM
CP_OUT
CTRL
OUTP
OUTM
Y0B
Y0
ADS6xxx
CLKM
CLKP
VCXO
CDCM7005
VCXO_INP
Reference Clock
S0238-02
S0168-07
CLKP
CLKM
CMOSClockInput
ADS6xxx
0.1 Fm
0.1 Fm
CLOCK BUFFER GAIN
ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com
Figure 36 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance
with this scheme is comparable with that of a low jitter sine wave clock source.
Figure 36. PECL Clock Drive Using CDCM7005
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin) connected to ground with a
0.1- µ F capacitor, as shown in Figure 37 .
Figure 37. Single-Ended Clock Driving Circuit
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input.
When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is
increased. Hence, it is recommended to use large clock amplitude. As shown by Figure 21 , use clock amplitude
greater than 1V pp to avoid performance degradation.
In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock
amplitude. The gain can be set by programming the register bits < CLKIN GAIN> (Table 12 ) and increases
monotonically from Gain 0 to Gain 5 settings. Table 20 shows the minimum clock amplitude supported for each
gain setting.
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