Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- TIMING SPECIFICATIONS
- SERIAL INTERFACE TIMING CHARACTERISTICS
- RESET TIMING
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- THEORY OF OPERATION
- ANALOG INPUT
- INPUT COMMON MODE
- REFERENCE
- COARSE GAIN AND PROGRAMMABLE FINE GAIN
- CLOCK INPUT
- CLOCK BUFFER GAIN
- POWER DOWN MODES
- POWER SUPPLY SEQUENCING
- DIGITAL OUTPUT INTERFACE
- OUTPUT BIT ORDER
- MSB/LSB FIRST
- OUTPUT DATA FORMATS
- LVDS CURRENT CONTROL
- LVDS INTERNAL TERMINATION
- CAPTURE TEST PATTERNS
- OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
- DEFINITION OF SPECIFICATIONS
2-WIRE INTERFACE - 14 × SERIALIZATION
ADS6425
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......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009
Figure 39. 2-Wire Interface 12 × Serialization
In 14 × serialization, two zero bits are padded to the 12-bit ADC data on the MSB side and the combined 14-bit
data is serialized and output over two LVDS pairs. A frame clock at 1 × sample frequency is also available with an
SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5 × sample frequency. The output data
rate will be 7 × Sample frequency as 7 data bits are output every clock cycle on each wire. Each ADC sample is
sent over the 2 wires as byte-wise or bit-wise or word-wise.
Using the 14 × serialization makes it possible to upgrade to a 14-bit ADC in the 64xx family in the future
seamlessly, without requiring any modification to the receiver capture logic design.
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