Datasheet

C001
C002
CAPTURE TEST PATTERNS
ADS6425
www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009
Figure 42. LVDS Data Eye Diagram with 5-pF Load Capacitance (No Internal Termination)
Figure 43. LVDS Data Eye Diagram with 10-pF Load Capacitance (100 Ω Internal Termination)
The ADS6425 outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is
recommended to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB.
This ensures sufficient setup/hold times for a reliable capture by the receiver.
The DESKEW is a 1010... or 0101... pattern output on the serial data lines that can be used to verify if the
receiver capture clock edge is positioned correctly. This may be useful in case there is some skew between
DCLK and serial data inside the receiver. Once deserialized, it is required to ensure that the parallel data is
aligned to the frame boundary. The SYNC test pattern can be used for this. For example, in the 1-wire interface,
the SYNC pattern is 6 '1's followed by 6 '0's (from MSB to LSB). This information can be used by the receiver
logic to shift the deserialized data till it matches the SYNC pattern.
In addition to DESKEW and SYNC, the ADS6425 includes other test patterns to verify correctness of the capture
by the receiver such as all zeros, all ones and toggle. These patterns are output on all four channel data lines
simultaneously. Some patterns like custom and sync are affected by the type of interface selected, serialization
and bit order.
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 45
Product Folder Link(s): ADS6425