Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- TIMING SPECIFICATIONS
- SERIAL INTERFACE TIMING CHARACTERISTICS
- RESET TIMING
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- THEORY OF OPERATION
- ANALOG INPUT
- INPUT COMMON MODE
- REFERENCE
- COARSE GAIN AND PROGRAMMABLE FINE GAIN
- CLOCK INPUT
- CLOCK BUFFER GAIN
- POWER DOWN MODES
- POWER SUPPLY SEQUENCING
- DIGITAL OUTPUT INTERFACE
- OUTPUT BIT ORDER
- MSB/LSB FIRST
- OUTPUT DATA FORMATS
- LVDS CURRENT CONTROL
- LVDS INTERNAL TERMINATION
- CAPTURE TEST PATTERNS
- OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
- DEFINITION OF SPECIFICATIONS
ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 .........................................................................................................................................................
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Table 23. Test Patterns
PATTERN DESCRIPTION
All zeros Outputs logic low.
All ones Outputs logic high.
Toggle Outputs toggle pattern - < D11-D0 > alternates between 101010101010 and 010101010101 every clock cycle.
Outputs a 12-bit custom pattern. The 12-bit custom pattern can be specified into two serial interface registers.
Custom
In the 2-wire interface, each code is sent over the 2 wires depending on the serialization and bit order.
Sync Outputs a sync pattern.
Deskew Outputs deskew pattern. Either < D11-D0 > = 101010101010 OR < D11-D0 > = 010101010101 every clock cycle.
Table 24. SYNC Pattern
INTERFACE OPTION SERIALIZATION SYNC PATTERN ON EACH WIRE
12 X MSB-111111000000- LSB
1-Wire
14 X MSB-11111110000000- LSB
12 X MSB-111000- LSB
2-Wire
14 X MSB-1111000- LSB
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