Datasheet

ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com
Table 28. Timings for 2-Wire Interface, SDR Bit Clock
DATA SETUP TIME, t
su
DATA HOLD TIME, t
h
t
delay
SAMPLING
ns ns ns
SERIALIZATION FREQUENCY
MSPS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 1.0 1.2 1.1 1.3 F
s
≥ 40 MSPS
40 1.8 2.0 1.9 2.1 3.4 4.4 5.4
12 ×
20 3.9 4.1 3.8 4.1 F
s
< 40 MSPS
10 8.2 8.4 7.8 8.2 3.7 5.2 6.7
65 0.8 1.0 1.0 1.2 F
s
≥ 40 MSPS
40 1.5 1.7 1.6 1.8 3.4 4.4 5.4
14 ×
20 3.4 3.6 3.3 3.5 F
s
< 40 MSPS
10 6.9 7.2 6.6 6.9 3.7 5.2 6.7
Table 29. Output Jitter (applies to all interface options)
BIT CLOCK JITTER, CYCLE-CYCLE FRAME CLOCK JITTER, CYCLE-CYCLE
SAMPLING FREQUENCY
ps, peak-peak ps, peak-peak
MSPS
MIN TYP MAX MIN TYP MAX
≥ 65 350 75
48 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS6425