Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- TIMING SPECIFICATIONS
- SERIAL INTERFACE TIMING CHARACTERISTICS
- RESET TIMING
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- THEORY OF OPERATION
- ANALOG INPUT
- INPUT COMMON MODE
- REFERENCE
- COARSE GAIN AND PROGRAMMABLE FINE GAIN
- CLOCK INPUT
- CLOCK BUFFER GAIN
- POWER DOWN MODES
- POWER SUPPLY SEQUENCING
- DIGITAL OUTPUT INTERFACE
- OUTPUT BIT ORDER
- MSB/LSB FIRST
- OUTPUT DATA FORMATS
- LVDS CURRENT CONTROL
- LVDS INTERNAL TERMINATION
- CAPTURE TEST PATTERNS
- OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
- DEFINITION OF SPECIFICATIONS
DIGITAL CHARACTERISTICS
ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 .........................................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25 ° C, min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD =
LVDD = 3.3V, sampling rate = 125MSPS, 50% clock duty cycle, – 1dBFS differential analog input, internal reference mode
(unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Fin = 10 MHz 88
Fin = 50 MHz 70 81
THD Total harmonic distortion Fin = 100 MHz 84 dBc
Fin = 170 MHz 73
Fin = 230 MHz 72
ENOB Effective number of bits Fin = 50 MHz 10.8 11.4 Bits
F1= 46.09 MHz, F2 = 50.09 MHz 90
IMD Two-tone intermodulation distortion dBFS
F1= 185.09 MHz, F2 = 190.09 MHz 82
Near channel, Frequency of interfering signal
92
= 10 MHz
Cross-talk dBFS
Far channel, Frequency of interfering signal
105
= 10 MHz
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = LVDD = 3.3V, I
O
= 3.5mA, R
LOAD
= 100 Ω
(1)
.
All LVDS specifications are characterized, but not tested at production.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS
High-level input voltage 2.4 V
Low-level input voltage 0.8 V
High-level input current 10 µ A
Low-level input current 10 µ A
Input capacitance 4 pF
DIGITAL OUTPUTS
High-level output voltage 1375 mV
Low-level output voltage 1025 mV
|V
OD
| Output differential voltage 250 350 450 mV
V
OS
Output offset voltage Common-mode voltage of OUTP and OUTM 1200 mV
Output capacitance Output capacitance inside the device, from either output to ground 2 pF
(1) I
O
refers to the LVDS buffer current setting, R
LOAD
is the external differential load resistance between the LVDS output pair
6 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS6425