Datasheet

TIMING SPECIFICATIONS
(1)
ADS6425
www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009
Typical values are at 25 ° C, min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD =
LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 V
PP
clock amplitude, C
L
= 5 pF
(2)
, I
O
= 3.5 mA,
R
L
= 100 Ω
(3)
, no internal termination, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
J
Aperture jitter Uncertainty in the sampling instant 250 fs rms
Interface: 2-wire, DDR bit clock, 12x serialization
(4)
Measured from zero crossing of data transitions to
t
su
Data setup time
(5) (6)
0.4 0.6 ns
zero crossing of bit clock
Measured from zero crossing of bit clock to zero
t
h
Data hold time
(5) (6)
0.5 0.7 ns
crossing of data transitions
Measured from zero-cross of frame clock rising
t
su
Frame setup time 0.4 0.6 ns
edge to zero-cross of bit clock rising edge
Measured from zero-cross of bit clock falling edge
t
h
Frame hold time 0.5 0.7 ns
to zero-cross of frame clock falling edge
Input clock rising edge cross-over to frame clock
t
pd_clk
Clock propagation delay
(4)
3.6 4.4 5.2 ns
rising edge cross-over
Bit clock cycle-cycle jitter
(6)
350 ps pp
Frame clock cycle-cycle jitter
(6)
75 ps pp
Below specifications apply for 5 MSPS ≤ Fs ≤ 125 MSPS and all interface options.
Delay from rising edge of input clock to the actual
t
A
Aperture delay 1 2 3 ns
sampling instant
Aperture delay variation,
Within the same device -250 250 ps
channel-channel
Time for a sample to propagate to the ADC output Clock
ADC Latency
(7)
12
Figure 1 cycles
Time to valid data after coming out of global power
100 µ s
down
Wake up time Time to valid data after input clock is re-started 100 µ s
Time to valid data after coming out of channel clock
200
standby cycles
Data rise time measured from – 100 mV to +100
t
RISE
Data rise time 50 100 200 ps
mV
t
FALL
Data fall time Data fall time measured from +100 mV to – 100 mV 50 100 200 ps
t
RISE
Bit clock and frame clock rise time Rise time measured from – 100mV to +100mV 50 100 200 ps
t
FALL
Bit clock and frame clock fall time Fall time measured from +100mV to – 100mV 50 100 200 ps
LVDS Bit clock duty cycle 45% 50% 55%
LVDS Frame clock duty cycle 47% 50% 53%
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) C
L
is the external single-ended load capacitance between each output pin and ground.
(3) I
o
refers to the LVDS buffer current setting; R
L
is the external differential load resistance between the LVDS output pair.
(4) Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.
(5) Timing parameters are measured at the end of a 2 inch pcb trace (100- Ω characteristic impedance) terminated by R
L
and C
L
.
(6) Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(7) Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as
shown in Table 25
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