Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- TIMING SPECIFICATIONS
- SERIAL INTERFACE TIMING CHARACTERISTICS
- RESET TIMING
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- THEORY OF OPERATION
- ANALOG INPUT
- INPUT COMMON MODE
- REFERENCE
- COARSE GAIN AND PROGRAMMABLE FINE GAIN
- CLOCK INPUT
- CLOCK BUFFER GAIN
- POWER DOWN MODES
- POWER SUPPLY SEQUENCING
- DIGITAL OUTPUT INTERFACE
- OUTPUT BIT ORDER
- MSB/LSB FIRST
- OUTPUT DATA FORMATS
- LVDS CURRENT CONTROL
- LVDS INTERNAL TERMINATION
- CAPTURE TEST PATTERNS
- OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
- DEFINITION OF SPECIFICATIONS
DCLKP
DCLKM
CLKM
CLKP
FCLKM
FCLKP
DOP
DOM
Sample N–1
t
A
t
PD_CLK
Sample
N
Sample
N+11
Sample
N+12
Sample
N+13
Input
Signal
Input
Clock
Bit
Clock
Output
Data
Frame
Clock
D11 D11D7 D7D3 D3D9 D9D5 D5D1 D1D10 D10D6 D6D2 D2D8 D8D4 D4D0 D0
Latency 12 Clocks
Sample N
T0105-03
BitClock
DCLKP
OutputData
(differential)
DA,DB,DC,DD
t
su
t
h
t
h
t
su
DCLKM
Dn+1
Dn
t
su
t
h
FCLKP
FCLKM
FrameClock
P
M
ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 .........................................................................................................................................................
www.ti.com
Figure 1. Latency
Figure 2. LVDS Timings
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