Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal VQFN 64

ADS6445, ADS6444

ADS6443, ADS6442

www.ti.com

SLAS531B –MAY 2007–REVISED DECEMBER 2009

QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

Check for Samples: ADS6445, ADS6444, ADS6443, ADS6442

FEATURES

• Pin Compatible 12-Bit Family (ADS642X -

SLAS532A)

• Maximum Sample Rate: 125 MSPS

• Feature Compatible Dual Channel Family

• 14-Bit Resolution with No Missing Codes

(ADS624X - SLAS542A, ADS644X - SLAS543A)

• Simultaneous Sample and Hold

• 3.5dB Coarse Gain and up to 6dB

APPLICATIONS

Programmable Fine Gain for SFDR/SNR

• Base-Station IF Receivers

Trade-Off

• Diversity Receivers

• Serialized LVDS Outputs with Programmable

• Medical Imaging

Internal Termination Option

• Test Equipment

• Supports Sine, LVCMOS, LVPECL, LVDS Clock

Inputs and Amplitude down to 400 mV

Table 1. ADS64XX Quad Channel Family

• Internal Reference with External Reference

125 MSPS 105 MSPS 80 MSPS 65 MSPS

Support

ADS644X

ADS6445 ADS6444 ADS6443 ADS6442

• No External Decoupling Required for

14 Bit

References

ADS642X

ADS6425 ADS6424 ADS6423 ADS6422

12 Bit

• 3.3-V Analog and Digital Supply

• 64 QFN Package (9 mm × 9 mm)

Table 2. Performance Summary

ADS6445 ADS6444 ADS6443 ADS6442

Fin = 10MHz (0 dB gain) 87 91 92 93

SFDR, dBc

Fin = 170MHz (3.5 dB gain) 79 83 84 84

Fin = 10MHz (0 dB gain) 73.4 73.4 74.2 74.3

SINAD, dBFS

Fin = 170MHz (3.5 dB gain) 68.3 69.3 69.4 70

Power, per channel, mW 420 340 300 265

DESCRIPTION

The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65

MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in

a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device

includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR.

In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it

possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing

receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling

frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit

clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and

bit clocks are also transmitted as LVDS outputs.

The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and

internal termination options. These can be used to widen eye-openings and improve signal integrity, easing

capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (81 pages)

PAGE 1
ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS Check for Samples: ADS6445, ADS6444, ADS6443, ADS6442 FEATURES • 1 • • • • • • • • • • Maximum Sample Rate: 125 MSPS 14-Bit Resolution with No Missing Codes Simultaneous Sample and Hold 3.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage 3.0 3.3 3.6 V LVDD LVDS Buffer supply voltage 3.0 3.3 3.6 V ANALOG INPUTS Differential input voltage range 2 Input common-mode voltage Vpp 1.5 ±0.1 Voltage applied on VCM in external reference mode 1.45 1.50 V 1.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted).
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 DIGITAL CHARACTERISTICS The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = LVDD = 3.3V, IO = 3.5mA, RLOAD = 100Ω (1). All LVDS specifications are characterized, but not tested at production. PARAMETER ASD6445/ADS6444 ADS6443/ADS6442 TEST CONDITIONS MIN TYP UNIT MAX DIGITAL INPUTS High-level input voltage 2.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com TIMING SPECIFICATIONS (1) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TIMING SPECIFICATIONS (1) (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com Sample N+13 Sample N+12 Sample N+11 Sample N Input Signal tA Input Clock CLKM CLKP tPD_CLK Latency 12 Clocks DCLKP Bit Clock DCLKM Output Data DOM DOP D13 D12 D11 D10 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 Sample N–1 Frame Clock D6 D5 D4 D3 D2 D1 D0 Sample N FCLKM FCLKP T0105-04 Figure 1.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 DEVICE PROGRAMMING MODES ADS644X offers flexibility with several programmable features that are easily configured. The device can be configured independently using either parallel interface control or serial interface programming. In addition, the device supports a third configuration mode, where both the parallel interface and the serial control registers are used.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com Table 4. Priority Between Parallel Pins and Serial Registers PIN FUNCTIONS SUPPORTED PRIORITY As described in Table 8 to Table 11 Register bits can control the modes only if the register bit is high. If bit is low, then the control voltage on these parallel pins determines the function. PDN Global Power Down Register bit controls global power down only if PDN pin is low.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 DESCRIPTION OF PARALLEL PINS Table 5. SCLK, SDATA Control Pins SCLK SDATA LOW LOW NORMAL conversion. DESCRIPTION LOW HIGH SYNC – ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the deserialized data to the frame boundary. See Capture Test Patterns for details.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com Table 11. CFG4 Control Pin CFG4 DESCRIPTION 0 (default) + 200mV MSB First and 2s complement (3/6) LVDD +/- 200mV MSB First and offset binary (5/6) LVDD +/- 200mV LSB First and offset binary LVDD - 200mV LSB First and 2s complement SERIAL INTERFACE The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 Register Address SDATA A4 A3 A2 A1 Register Data A0 D10 D9 D8 D7 D6 t(SCLK) D5 D4 D3 D2 D1 D0 t(DH) t(DSU) SCLK t(SLOADH) t(SLOADS) SEN RESET T0109-03 Figure 4.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, unless otherwise noted.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 SERIAL REGISTER MAP Table 12.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com DESCRIPTION OF SERIAL REGISTERS Table 13. Serial Register A REGISTER ADDRESS A4 - A0 D10 S/W RESET 00 (1) BITS (1) D9 D8 0 0 D7 0 D6 D5 0 INTERNAL OR EXTERNAL D4 D3 POWER DOWN CH D POWER DOWN CHC D2 POWER DOWN CH B D1 D0 POWER DOWN CH A GLOBAL POWER DOWN After a hardware or software reset, all register bits are cleared to 0.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 Table 14. Serial Register B REGISTER ADDRESS BITS (1) A4 - A0 D10 D9 D8 D7 04 0 0 0 0 (1) D6 D5 D4 D3 D2 INPUT CLOCK BUFFER GAIN CONTROL D1 D0 0 0 After a hardware or software reset, all register bits are cleared to 0.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com Table 16. Serial Register D REGISTER ADDRESS A4 - A0 BITS (1) D10 D9 D8 D7 (1) D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 CUSTOM PATTERN (LOWER 11 BITS) 0B After a hardware or software reset, all register bits are cleared to 0. D10 - D0 Lower 11 bits of custom pattern … Table 17.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 D5 Coarse gain control 0 0 dB Coarse gain (full-scale range = 2.0 VPP) 1 3.5dB Coarse gain (full-scale range = 1.34 VPP) D6 MSB or LSB First selection 0 MSB First 1 LSB First D7 Byte/bit wise outputs (only when 2-wire is selected) 0 Byte wise 1 Bit wise D10 Over-ride bit. All the functions in register 0x0D can also be controlled using the parallel control pins.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 00010 200 Ω 00100 250 Ω 01000 333 Ω 10000 500 Ω www.ti.com Any combination of above bits can also be programmed, resulting in a parallel combination of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω 100 Ω 00101 Table 20.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued) PINS NAME NO. I/O NO. OF PINS DESCRIPTION INA_P, INA_M 12,11 I 2 Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not float. INB_P, INB_M 15,14 I 2 Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not float.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued) PINS NAME PAD NO. 0 I/O NO. OF PINS DESCRIPTION 1 Connect to ground plane using multiple vias. Refer to Board Design Considerations in the application section.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued) PINS NAME NO. I/O NO. OF PINS DESCRIPTION INA_P, INA_M 12,11 I 2 Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not float. INB_P, INB_M 15,14 I 2 Differential input signal pair, channel B.If unused, the pins should be tied to VCM. Do not float. INC_P, INC_M 34,35 I 2 Differential input signal pair, channel C.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 75 92 90 74 Gain = 3.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) CMRR vs FREQUENCY 78 fIN = 50.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) ADS6444 (Fsrated = 105 MSPS) FFT for 10 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 SFDR = 91.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 92 76 90 75 74 86 73 SNR − dBFS Gain = 3.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) CMRR vs FREQUENCY 76 fIN = 70.1 MHz External Reference Mode 74 SNR 83 82 72 70 SFDR 81 80 1.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) ADS6443 (Fsrated = 80 MSPS) FFT for 10 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 SFDR = 91 dBc SINAD = 74.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 96 76 94 75 92 74 88 Gain = 3.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE 78 fIN = 50.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) CMRR vs FREQUENCY 76 fIN = 50.1 MHz External Reference Mode 74 SNR 92 72 SFDR 90 70 88 86 1.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) ADS6442 (Fsrated = 65 MSPS) FFT for 10 MHz INPUT SIGNAL FFT for 50 MHz INPUT SIGNAL 0 SFDR = 92.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 96 76 94 75 92 74 88 Gain = 3.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) CMRR vs FREQUENCY 76 fIN = 50.1 MHz External Reference Mode 94 74 92 72 90 70 SFDR 88 86 1.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of quad channel, 14-bit pipeline ADC based on switched capacitor architecture in CMOS technology. The conversion is initiated simultaneously by all the four channels at the rising edge of the external input clock.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 1 Magnitude − dB 0 −1 −2 −3 −4 −5 −6 0 100 200 300 400 500 fIN − Input Frequency − MHz 600 700 G073 Figure 83. Analog Input Bandwidth (represented by magnitude of TF_ADC, see Figure 85 ) Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com F1 Freq = 50 MHz S(1, 1) = 0.967 / –13.241 Impedance = 62.211 – j421.739 1000 F1 Frequency = 50 MHz Mag(Zin1) = 426.302 900 700 F2 Frequency = 400 MHz Mag(Zin1) = 65.193 600 F1 500 S(1, 1) Magnitude of Zin -- W 800 400 F2 300 200 F1 F2 100 0 0 50 100 150 200 250 300 350 400 450 500 fI -- Input Frequency -- MHz Frequency (100 kHz to 500 MHz) F2 Freq = 400 MHz S(1, 1) = 0.273 / –59.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TF_ADC 0.1 mF ADS6xxx 5W INP 0.1 mF 25 W 25 W INM 5W 1:1 VCM S0256-01 Figure 85. Single Transformer Drive Circuit At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com Using Differential Amplifier Drive Circuits Figure 87 shows a drive ciruit using a differential amplifier (TI's THS4509) to convert a single-ended input to differential output that can be interfaced to the ADC input pins. In addition to the single-ended to differential conversion, the amplifier also provides gain (10 dB in Figure 87).
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 INTREF Internal Reference VCM 1 kW INTREF 4 kW EXTREF REFM REFP ADS6xxx S0165-04 Figure 88. Reference Section Internal Reference When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog input pins.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the SFDR improvement is significant with marginal degradation in SINAD. The gains can be programmed using the register bits (refer to Table 18) and (refer to Table 17).
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 0.1 mF CLKP Differential Sine-Wave or PECL or LVDS Clock Input 0.1 mF CLKM ADS6xxx S0167-05 Figure 90. Differential Clock Driving Circuit Figure 91 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance with this scheme is comparable with that of a low jitter sine wave clock source.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com DIGITAL OUTPUT INTERFACE The ADS644X offers several flexible output options making it easy to interface to an ASIC or an FPGA. Each of these options can be easily programmed using either parallel pins or the serial interface.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 2-WIRE INTERFACE - 14× SERIALIZATION The 14-bit ADC data is serialized and output over two LVDS pairs. A frame clock at 1× sample frequency is also available with an SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5× sample frequency. The output data rate will be 7 × sample frequency as 7 data bits are output every clock cycle on each wire.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 Input Clock, CLK Freq = Fs Frame Clock, FCLK Freq = 0.5 ´ Fs In Byte-Wise Mode Bit Clock – DDR, DCLK Freq = 3.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com OUTPUT BIT ORDER In the 2-wire interface, three types of bit order are supported - byte-wise, bit-wise and word-wise. Byte-wise: Each 14-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 7 LSB bits D6 - D0 and wires DA1, DB1, DC1 and DD1 carry the 7 MSB bits. Bit-wise: Each 14-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 7 even bits (D0,D2,D4..
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 C001 Figure 97. LVDS Data Eye Diagram with 5-pF Load Capacitance (No Internal Termination) C002 Figure 98.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com CAPTURE TEST PATTERNS ADS644X outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is recommended to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB. This ensures sufficient setup/hold times for a reliable capture by the receiver. The DESKEW is a 1010... or 0101...
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES Setup, hold, and other timing parameters are specified across sampling frequencies and for each type of output interface in the following tables. Table 28 to Table 31: Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, CL = 5 pF, IO = 3.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com Table 30. Timings for 2-Wire Interface, SDR Bit Clock SERIALIZATION 14× 16× DATA SETUP TIME, tsu ns DATA HOLD TIME, th ns SAMPLING FREQUENCY MSPS MIN TYP MIN TYP 65 0.8 1 1 1.2 40 1.5 1.7 1.6 1.8 20 3.4 3.6 3.3 3.5 10 6.9 7.2 6.6 6.9 65 0.65 0.85 0.8 1.0 40 1.3 1.5 1.4 1.6 20 2.8 3.0 2.8 3.0 10 6.0 6.3 5.8 6.1 MAX tdelay ns MAX MIN TYP MAX Fs ≥ 40 MSPS 3.4 4.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give optimum performance, provided the analog, digital and clock sections of the board are cleanly partitioned. Refer to the EVM User Guide (SLAU196) for board layout schemes. Supply Decoupling As the ADS644X already includes internal decoupling, minimal external decoupling can be used without loss in performance.
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay will be different across channels.
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ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com THD + 10Log10 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 PS PD (6) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
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ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com REVISION HISTORY Changes from Revision A (June 2007) to Revision B Page • Added Frame setup time .................................................................................................................................................... 10 • Added Frame hold time ...............................................................................................................................................
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PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS6442IRGCR VQFN RGC 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS6442IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS6443IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS6442IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS6442IRGCT VQFN RGC 64 250 336.6 336.6 28.6 ADS6443IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS6443IRGCT VQFN RGC 64 250 336.6 336.6 28.6 ADS6444IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS6444IRGCT VQFN RGC 64 250 336.6 336.6 28.
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