Datasheet

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12-Bit 3µs Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 333k SAMPLES PER SECOND

● STANDARD ±10V AND ±5V INPUT RANGES

● DC PERFORMANCE OVER TEMP:

No Missing Codes

1/2LSB Integral Linearity Error

3/4LSB Differential Linearity Error

● AC PERFORMANCE OVER TEMP:

72dB Signal-to-Noise Ratio

80dB Spurious-Free Dynamic Range

–80dB Total Harmonic Distortion

● INTERNAL SAMPLE/HOLD, REFERENCE,

CLOCK, AND THREE-STATE OUTPUTS

● POWER DISSIPATION: 215mW max

● PACKAGE: 24-Pin Single-Wide DIP

24-Lead SOIC

Comparator

Control

Logic

Internal

Ref

Reference

Out

±5V

±10V

CDAC

SAR

BUSY

Three

State

Parallel

Output

Data

Bus

Clock

Output

Latches

And

Three

State

Drivers

DESCRIPTION

The ADS7800 is a complete 12-bit sampling analog-to-

digital (A/D) converter using state-of-the-art CMOS

structures. It contains a complete 12-bit successive

approximation A/D converter with internal sample/hold,

reference, clock, digital interface for microprocessor

control, and three-state output drivers.

The ADS7800 is specified at a 333kHz sampling rate.

Conversion time is factory set for 2.70µs max over

temperature, and the high-speed sampling input stage

insures a total acquisition and conversion time of 3µs

max over temperature. Precision, laser-trimmed scaling

resistors provide industry-standard input ranges of ±5V

or ±10V.

AC and DC performance are completely specified. Two

grades based on linearity and dynamic performance are

available to provide the optimum price/performance fit in

a wide range of applications.

The 24-pin ADS7800 is available in plastic and side-

braze hermetic 0.3" wide DIPs, and in an SOIC package.

It operates from a +5V supply and either a –12V or –15V

supply. The ADS7800 is available in grades specified

over 0°C to +70°C and –40°C to +85°C temperature

ranges.

ADS7800

SBAS001A – OCTOBER 1989 – REVISED FEBRUARY 2004

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

Summary of content (20 pages)

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ADS7800 SBAS001A – OCTOBER 1989 – REVISED FEBRUARY 2004 12-Bit 3µs Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 333k SAMPLES PER SECOND ● STANDARD ±10V AND ±5V INPUT RANGES ● DC PERFORMANCE OVER TEMP: No Missing Codes 1/2LSB Integral Linearity Error 3/4LSB Differential Linearity Error ● AC PERFORMANCE OVER TEMP: 72dB Signal-to-Noise Ratio 80dB Spurious-Free Dynamic Range –80dB Total Harmonic Distortion ● INTERNAL SAMPLE/HOLD, REFERENCE, CLOCK, AND THREE-STATE OUTPUTS ● POWER DISSIPATION:
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SPECIFICATIONS ELECTRICAL At TA = TMIN to TMAX, Sampling Frequency, fS, = 333kHz, –VS = –15V, VS = +5V, unless otherwise specified. ADS7800JP/JU/AH PARAMETER CONDITIONS MIN TYP RESOLUTION ±10V Range ±5V Range 4.4 2.9 ±10V/±5V 6.3 4.2 333 2.5 2.6 380 Conversion Alone Acquisition + Conversion DC ACCURACY Full Scale Error (1) Full Scale Error Drift Integral Linearity Error Differential Linearity Error No Missing Codes Bipolar Zero(1) Bipolar Zero Drift Power Supply Sensitivity * * * * * * * 2.
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SPECIFICATIONS (CONT) ELECTRICAL At TA = TMIN to TMAX, Sampling Frequency, fS, = 333kHz, –VS = –15V, VS = +5V, unless otherwise specified. ADS7800JP/JU/AH PARAMETER TEMPERATURE RANGE Specification Operating Storage CONDITIONS MIN JP/JU/KP/KU AH/BH JP/KP/JU/KU 0 –40 –40 –65 TYP ADS7800KP/KU/BH MAX MIN +70 +85 +85 +150 * * * * TYP MAX UNITS * * * * °C °C °C °C * Same as specification for ADS7800JP/JU/AH. NOTES: (1) Adjustable to zero with external potentiometer.
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PIN ASSIGNMENTS PIN # NAME 1 4 PIN CONFIGURATION Top View DESCRIPTION IN1 ±10V Analog Input. Connected to GND for ±5V range. DIP/SOIC 2 IN2 ±5V Analog Input. Connected to GND for ±10V range. 3 REF +2V Reference Output. Bypass to GND with 22µF to 47µF Tantalum. Buffer for external loads. IN1 1 24 VSA 4 AGND Analog Ground. Connect to pin 13. IN2 2 23 VSD 5 D11 Data Bit 11. Most Significant Bit (MSB). 6 D10 Data Bit 10. REF 3 22 –VS 7 D9 Data Bit 9.
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TYPICAL PERFORMANCE CURVES At +VS = +5V, –VS = –15V, and TA = +25°C, unless otherwise noted. All plots use 1024 point FFTs.
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THEORY OF OPERATION +5V The ADS7800 combines the advantages of advanced CMOS technology (logic density, stable capacitors, and good analog switches) with Burr-Brown’s proven skills in lasertrimmed thin-film resistors to provide a complete sampling A/D converter. 47µF A basic charge-redistribution successive approximation architecture converts analog input voltages into digital words. Figure 1 shows the operation of a simplified 3-bit charge redistribution A/D.
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R/C tB BUSY tDBC tC Converter Acquisition Mode tAP Conversion Acquisition Conversion FIGURE 3. Acquisition and Conversion Timing. PARAMETER tDBC tB tAP ∆tAP tC BUSY delay from R/C BUSY Low Aperture Delay Aperture Jitter Conversion Time R/C 1 0 0 X 1↓0 1 HBE BUSY X 0 0 1 1 1 0 0 0 X 1 1↓0 0 X 1 1 1 X 1 1 1 0 OPERATION None - Outputs in Hi-Z State. Holds Signal and Initiates Conversion. Output Three-State Buffers Enabled once Conversion has Finished. Enable Hi-Byte in 8-bit Bus Mode.
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INTERNAL CLOCK The ADS7800 has an internal clock that is factory trimmed to achieve a typical conversion time of 2.47µs, and a maximum conversion time over the full operating temperature range of 2.7µs. No external adjustments are required, and with the guaranteed maximum acquisition time of 300ns, throughput performance is assured with convert pulses as close as 3µs. 1 ADS7800 ±5V Input 2 FIGURE 5. ±5V Range Without Trims.
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R/C tW tB BUSY tDBC tAP Converter Mode Acquire tDBE tAP Convert Acquire tC tA tDD Convert tHDR and tHL Data BUS Hi-Z State Data Valid Hi-Z State Data Valid Hi-Z State FIGURE 7. Read Mode: R/C Pulse HIGH— Outputs Enabled Only When R/C is High. SYMBOL tW tDBC PARAMETER MIN TYP R/C Pulse Width 40 10 MAX UNITS ns BUSY delay from R/C 80 150 ns tB BUSY LOW 2.5 2.7 µs tAP Aperture Delay 13 ns ∆tAP Aperture Jitter 150 ps, rms tC 2.
PAGE 10
converter if at all possible. A ground plane is usually the best solution for preserving dynamic performance and reducing noise coupling into sensitive converter circuits. Where any compromises must be made, the common return of the analog input signal should be referenced to pin 4, AGND, on the ADS7800, which prevents any voltage drops that might occur in the power supply common returns from appearing in series with the input signal.
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Next, although the data outputs are forced into a Hi-Z state during conversion, fast bus transients can still be capacitively coupled into the ADS7800. If the data bus experiences fast transients during conversion, these transients can be attenuated by adding a logic buffer to the data outputs. The BUSY output can be used to enable the buffer.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 26-Dec-2011 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS7800JU/1K Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7800JU/1K SOIC DW 24 1000 367.0 367.0 45.
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MECHANICAL DATA MCDI046 – JANUARY 2002 JDN (R–CDIP–T24) CERAMIC SIDE-BRAZE DUAL-IN-LINE 1.212 (30,78) 1.188 (30,18) 24 13 0.310 (7,87) 0.280 (7,11) Index Area 1 12 0.060 (1,52) 0.038 (0,97) 0.010 (0,25) MIN 0.175 (4,45) 0.105 (2,67) E 0.325 (8,26) 0.290 (7,37) Base Plane Seating Plane D 0.065 (1,65) 0.030 (0,76) 0.021 (0,53) E 0.015 (0,38) E 0.055 (1,40) 0.025 (0,64) 0.100 (2,54) TYP 0°– 15° 0.175 (4,45) 0.125 (3,18) 0.012 (0,30) 0.008 (0,20) 0.300 (7,62) TYP 4204038/A 12/01 NOTES: A.
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