Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SOIC 28

Low-Power, 16-Bit, Sampling CMOS

ANALOG-to-DIGITAL CONVERTER

FEATURES

● 35mW max POWER DISSIPATION

● 50µW POWER-DOWN MODE

● 25µs max ACQUISITION AND CONVERSION

● ±1.5LSB max INL

● DNL: 16 Bits, No Missing Codes

● 86dB min SINAD WITH 1kHz INPUT

●

10V, 0V TO +5V, AND 0V TO +4V INPUT RANGES

● SINGLE +5V SUPPLY OPERATION

● PARALLEL AND SERIAL DATA OUTPUT

● PIN-COMPATIBLE WITH THE 12-BIT ADS7806

● USES INTERNAL OR EXTERNAL REFERENCE

● 0.3" DIP-28 AND SO-28

DESCRIPTION

The ADS7807 is a low-power, 16-bit, sampling Analog-to-

Digital (A/D) converter using state-of-the-art CMOS struc-

tures. It contains a complete 16-bit, capacitor-based, Suc-

cessive Approximation Register (SAR) A/D converter with

sample-and-hold, clock, reference, and microprocessor inter-

face with parallel and serial output drivers.

The ADS7807 can acquire and convert 16 bits to within

±1.5LSB in 25µs max while consuming only 35mW max.

Laser trimmed scaling resistors provide standard industrial

input ranges of ±10V and 0V to +5V. In addition, a 0V to +4V

range allows development of complete single-supply sys-

tems.

The ADS7807 is available in a 0.3" DIP-28 and SO-28, both

fully specified for operation over the industrial –40°C to

+85°C temperature range.

ADS7807

SBAS022D – NOVEMBER 1992 – REVISED NOVEMBER 2006

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CDAC

6kΩ

40kΩ

10kΩ

BUSY

Parallel

and

Serial

Data

Out

Comparator

Buffer

20kΩ

REF

Successive Approximation Register and Control Logic

Clock

Power

Down

BYTE

R/C

40kΩ

Internal

+2.5V Ref

Reference

Power-Down

Serial Data

Clock

Parallel Data

CAP

Serial Data

S7807

All trademarks are the property of their respective owners.

Summary of content (27 pages)

PAGE 1
ADS7807 AD S 780 7 ADS 780 7 SBAS022D – NOVEMBER 1992 – REVISED NOVEMBER 2006 Low-Power, 16-Bit, Sampling CMOS ANALOG-to-DIGITAL CONVERTER FEATURES DESCRIPTION ● 35mW max POWER DISSIPATION ● 50µW POWER-DOWN MODE ● 25µs max ACQUISITION AND CONVERSION ● ±1.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) ........................................................................... ±12V .......................................................................... ±5.5V .................................. VANA + 0.3V to AGND2 – 0.3V ......................................... Indefinite Short to AGND2, Momentary Short to VANA Ground Voltage Differences: DGND, AGND1, and AGND2 ............. ±0.3V VANA .....................................................
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ELECTRICAL CHARACTERISTICS (Cont.) At TA = –40°C to +85°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.
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PIN DESCRIPTIONS DIGITAL I/O PIN # NAME 1 2 3 4 5 6 7 8 9 R1IN AGND1 R2IN CAP REF AGND2 SB/BTC EXT/INT D7 10 11 12 13 14 15 16 17 18 19 20 21 22 D6 D5 D4 D3 DGND D2 D1 D0 DATACLK SDATA TAG BYTE R/C O O O I/O O I I I 23 CS I 24 BUSY O 25 26 27 28 PWRD REFD VANA VDIG I I DESCRIPTION Analog Input. See Figure 7. Analog Sense Ground. Analog Input. See Figure 7. Reference Buffer Output. 2.2µF tantalum capacitor to ground. Reference Input/Output. 2.2µF tantalum capacitor to ground.
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TYPICAL CHARACTERISTICS At TA = +25°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.
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BASIC OPERATION PARALLEL OUTPUT Figure 1a shows a basic circuit to operate the ADS7807 with a ±10V input range and parallel output. Taking R/C (pin 22) LOW for a minimum of 40ns (12µs max) will initiate a conversion. BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the output register is updated. If BYTE (pin 21) is LOW, the eight Most Significant Bits (MSBs) will be valid when BUSY rises; if BYTE is HIGH, the eight Least Significant Bits (LSBs) will be valid when BUSY rises.
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The ADS7807 will begin tracking the input signal at the end of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal. Refer to Tables II and III for a summary of CS , R/C, and BUSY states, and Figures 2 through 6 for timing diagrams. CS R/C BUSY OPERATION 1 X X None. Databus is in Hi-Z state. ↓ 0 1 Initiates conversion ‘n’. Databus remains in Hi-Z state. 0 ↓ 1 Initiates conversion ‘n’. Databus enters Hi-Z state. 0 1 ↑ Conversion ‘n’ completed.
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clock pulse. As a result, data can be read on the parallel port prior to reading the same data on the serial port, but data cannot be read through the serial port prior to reading the same data on the parallel port. PARALLEL OUTPUT To use the parallel output, tie EXT/INT (pin 8) HIGH and DATACLK (pin 18) LOW. SDATA (pin 19) should be left unconnected. The parallel output will be active when R/C (pin 22) is HIGH and CS (pin 23) is LOW. Any other combination of CS and R/C will tri-state the parallel output.
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SYMBOL DESCRIPTION t1 t2(1) t3(1) Convert Pulse Width Data Valid Delay after R/C LOW BUSY Delay from Start of Conversion BUSY LOW BUSY Delay after End of Conversion Aperture Delay Conversion Time Acquisition Time Bus Relinquish Time BUSY Delay after Data Valid Previous Data Valid after Start of Conversion Bus Access Time and BYTE Delay Start of Conversion to DATACLK Delay DATACLK Period Data Valid to DATACLK HIGH Delay Data Valid after DATACLK LOW Delay External DATACLK Period External DATACLK LOW Extern
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t7 + t8 CS or R/C(1) t14 DATACLK 1 t13 2 3 15 16 1 2 Bit 13 Valid Bit 1 Valid LSB Valid MSB Valid Bit 14 Valid t16 t15 MSB Valid Bit 14 Valid SDATA (Results from previous conversion.) BUSY NOTE: (1) If controlling with CS , tie R/C LOW. Data bus pins will remain Hi-Z at all times. If controlling with R/C, tie CS LOW. Data bus pins will be active when R/C is HIGH, and should be left unconnected. FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).
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INPUT RANGES EXTERNAL DATA CLOCK (During a Conversion) After conversion ‘n’ has been initiated, valid data from conversion ‘n – 1’ can be read and will be valid up to 12µs after the start of conversion ‘n’. Do not attempt to clock out data from 12µs after the start of conversion ‘n’ until BUSY (pin 24) rises; this will result in data loss. NOTE: For the best possible performance when using an external data clock, data should not be clocked out during a conversion.
PAGE 13
CALIBRATION SOFTWARE CALIBRATION To calibrate the offset and gain in software, no external resistors are required. However, to get the data sheet specifications for offset and gain, the resistors shown in Figure 7b are necessary. See the No Calibration section for more details on the external resistors. Refer to Table VIII for the range of offset and gain errors with and without the external resistors.
PAGE 14
The external resistors (see Figure 7b) may not be necessary in some applications. These resistors provide compensation for an internal adjustment of the offset and gain which allows calibration with a single supply. Not using the external resistors will result in offset and gain errors in addition to those listed in the Electrical Characteristics section. Offset refers to the equivalent voltage of the digital output when converting with the input grounded.
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200Ω 39.8kΩ VIN CDAC (0.3125V to 2.8125V) 20kΩ 9.9kΩ 66.5kΩ 40kΩ +5V 100Ω +2.5V +2.5V 200Ω 39.8kΩ CDAC (0.3125V to 2.8125V) 33.2kΩ 20kΩ 9.9kΩ 100Ω 40kΩ VIN +2.5V 200Ω +2.5V 39.8kΩ VIN CDAC (0.3125V to 2.8125V) 33.2kΩ 20kΩ 9.9kΩ 100Ω +2.5V 40kΩ +2.5V FIGURE 9. Circuit Diagrams Showing External and Internal Resistors. The internal reference has approximately an 8ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error (FSE = ±0.5% for low grade, ±0.
PAGE 16
The output of the buffer is capable of driving up to 1mA of current to a DC load. Using an external buffer will allow the internal reference to be used for larger DC loads and AC loads. Do not attempt to directly drive an AC load with the output voltage on CAP. This will cause performance degradation of the converter. 7000 5000 µs 4000 3000 2000 1000 0 1 10 100 “CAP” Pin Value (µF) FIGURE 11. Power-Down to Power-Up Time vs Capacitor Value on CAP.
PAGE 17
INTERMEDIATE LATCHES The ADS7807 does have tri-state outputs for the parallel port, but intermediate latches should be used if the bus will be active during conversions. If the bus is not active during conversion, the tri-state outputs can be used to isolate the A/D converter from other peripherals on the same bus. 581 Intermediate latches are beneficial on any monolithic A/D converter. The ADS7807 has an internal LSB size of 38µV.
PAGE 18
QSPI™ INTERFACING QSPI™ Figure 14 shows a simple interface between the ADS7807 and any QSPI equipped microcontroller. This interface assumes that the convert pulse does not originate from the microcontroller and that the ADS7807 is the only serial peripheral. ADS7807 PCS0 R/C PCS1 CS +5V EXT/INT SCK DATACLK MISO D7 (MSB) Convert Pulse QSPI™ CPOL = 0 CPHA = 0 ADS7807 R/C PCS0/SS MOSI SCK QSPI is a registered trademark of Motorola. BUSY FIGURE 15. QSPI Interface to the ADS7807.
PAGE 19
DSP56000 INTERFACING The DSP56000 serial interface has SPI compatibility mode with some enhancements. Figure 16 shows an interface between the ADS7807 and the DSP56000 which is very similar to the QSPI interface seen in Figure 14. As mentioned in the QSPI section, the DSP56000 must be programmed to enable the interface when a LOW to HIGH transition on SC1 is observed (BUSY going HIGH at the end of conversion).
PAGE 20
Revision History DATE REVISION 11/06 D PAGE SECTION 2 Electrical Characteristics 10 Table V DESCRIPTION Changed Analog Input Capacitance from 35pF to 45pF. Updated Table V and added PDIP package timing; page layout reflowed. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 20 ADS7807 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS7807U/1K Package Package Pins Type Drawing SOIC DW 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 32.4 Pack Materials-Page 1 11.35 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 18.67 3.1 16.0 32.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7807U/1K SOIC DW 28 1000 367.0 367.0 55.
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