Datasheet

ADS7808
3
SBAS018A
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
At T
A
= –40°C to +85°C, f
S
= 100kHz, V
DIG
= V
ANA
= +5V, using internal reference and fixed resistors shown in Figure 4, unless otherwise specified.
ADS7808U ADS7808UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Serial 12 bits
Binary Two's Complement or Straight Binary
Conversion results only available after completed conversion.
Selectable for internal or external data clock
SAMPLING DYNAMICS
Aperture Delay 40 ✻ ns
Aperture Jitter Sufficient to meet AC specs ✻ ns
Transient Response FS Step 2 ✻ µs
Overvoltage Recovery
(7)
150 ✻ ns
REFERENCE
Internal Reference Voltage No Load 2.48 2.5 2.52 ✻✻ ✻ V
Internal Reference Source Current 1 ✻ µA
(Must use external buffer)
External Reference Voltage Range 2.3 2.5 2.7 ✻✻ ✻ V
for Specified Linearity
External Reference Current Drain Ext. 2.5000V Ref 100 ✻ µA
DIGITAL INPUTS
Logic Levels
V
IL
–0.3 +0.8 ✻✻V
V
IH
(8)
+2.0 V
D
+0.3V ✻✻V
I
IL
V
IL
= 0V ±10 ✻ µA
I
IH
V
IH
= 5V ±10 ✻ µA
DIGITAL OUTPUTS
Data Format
Data Coding
Pipeline Delay
Data Clock
Internal EXT/INT LOW 2.3 ✻ MHz
(Output Only When
Transmitting Data)
External EXT/INT HIGH 0.1 10 ✻✻MHz
(Can Run Continually)
V
OL
I
SINK
= 1.6mA +0.4 ✻ V
V
OH
I
SOURCE
= 500µA+4 ✻ V
Leakage Current High-Z State, ±5 ✻ µA
V
OUT
= 0V to V
DIG
Output Capacitance High-Z State 15 15 pF
POWER SUPPLIES
Specified Performance
V
DIG
Must be ≤ V
ANA
+4.75 +5 +5.25 ✻✻ ✻ V
V
ANA
+4.75 +5 +5.25 ✻✻✻V
I
DIG
0.3 ✻ mA
I
ANA
16 ✻ mA
Power Dissipation: PWRD LOW V
DIG
= V
ANA
= 5V, f
S
= 100kHz 100 ✻ mW
PWRD HIGH 50 ✻ µW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻ °C
Derated Performance –55 +125 ✻✻ °C
Storage –65 +150 ✻✻°C
Thermal Resistance (
θ
JA
)
SO 75 ✻ °CW
✻ Specifications same as ADS7808U.
NOTES: (1) LSB means Least Significant Bit. For the ±10V input range, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and temperatures.
(3) As measured with fixed resistors in Figure 4. Adjustable to zero with external potentiometer. (4) For bipolar input ranges, full scale error is the worst case of
–Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and
includes the effect of offset error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes
the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which
Signal-to (Noise + Distortion) degrades to 60dB. (7) Recovers to specified performance after 2 x FS input overvoltage. (8) The minimum V
IH
level for the DATACLK
signal is 3V.