Datasheet

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Low-Power, Serial 12-Bit Sampling

ANALOG-TO-DIGITAL CONVERTER

DESCRIPTION

The ADS7812 is a low-power, single +5V supply, 12-bit

sampling analog-to-digital converter. It contains a complete

12-bit capacitor-based SAR A/D with a sample/hold, clock,

reference, and serial data interface.

The converter can be configured for a variety of input ranges

including ±10V, ±5V, 0V to 10V, and 0.5V to 4.5V. A high

impedance 0.3V to 2.8V input range is also available (input

impedance > 10MΩ). For most input ranges, the input

voltage can swing to +16.5V or –16.5V without damage to

the converter.

A flexible SPI compatible serial interface allows data to be

synchronized to an internal or external clock. The ADS7812

is specified at a 40kHz sampling rate over the –40°C to

+85°C temperature range. It is available in a 0.3" DIP-16 or

an SO-16 package.

FEATURES

● 20µs max CONVERSION TIME

● SINGLE +5V SUPPLY OPERATION

● PIN-COMPATIBLE WITH 16-BIT ADS7813

● EASY-TO-USE SERIAL INTERFACE

● 0.3" DIP-16 AND SO-16

● ±0.5LSB max INL AND DNL

● 72dB min SINAD

● USES INTERNAL OR EXTERNAL

REFERENCE

● MULTIPLE INPUT RANGES

● 35mW max POWER DISSIPATION

● NO MISSING CODES

● 50µW POWER DOWN MODE

ADS7812

8kΩ

(1)

CDAC

4kΩ

(1)

40kΩ

(1)

20kΩ

(1)

Internal

+2.5V Ref

Clock

EXT/INT

DATACLK

DATA

Successive Approximation Register and Control Logic

Serial

Data

Out

Comparator

Buffer

BUSY PWRD

CONV

REF

BUF

CAP

NOTE: (1) Actual value may vary ±30%.

APPLICATIONS

● DATA ACQUISITION SYSTEMS

● INDUSTRIAL CONTROL

● TEST EQUIPMENT

● DIGITAL SIGNAL PROCESSING

ADS7812

SBAS042A – MARCH 1997 – REVISED SEPTEMBER 2003

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

Summary of content (24 pages)

PAGE 1
ADS7812 ADS 781 ADS 781 2 2 SBAS042A – MARCH 1997 – REVISED SEPTEMBER 2003 Low-Power, Serial 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES ● ● ● ● ● ● ● ● ● ● ● ● DESCRIPTION 20µs max CONVERSION TIME SINGLE +5V SUPPLY OPERATION PIN-COMPATIBLE WITH 16-BIT ADS7813 EASY-TO-USE SERIAL INTERFACE 0.3" DIP-16 AND SO-16 ±0.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Analog Inputs: R1IN ......................................................................... ±16.5V R2IN ................................................ GND – 0.3V to +16.5V R3IN ......................................................................... ±16.5V REF ............................................ GND – 0.3V to VS + 0.3V CAP ............................................... Indefinite Short to GND Momentary Short to VS VS ...........
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SPECIFICATIONS (Cont.) At TA = –40°C to +85°C, fS = 40kHz, VS = +5V ±5%, using internal reference, unless otherwise specified.
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PIN CONFIGURATION PIN # NAME DESCRIPTION 1 R1IN Analog Input. See Tables I and IV. 2 GND Ground 3 R2IN Analog Input. See Tables I and IV. 4 R3IN Analog Input. See Tables I and IV. 5 BUF Reference Buffer Output. Connect to R1IN, R2IN, or R3IN, as needed. 6 CAP Reference Buffer Compensation Node. Decouple to ground with a 1µF tantalum capacitor in parallel with a 0.01µF ceramic capacitor. 7 REF Reference Input/Output. Outputs internal +2.5V reference via a series 4kΩ resistor.
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TYPICAL PERFORMANCE CURVES At TA = +25°C, fS = 40kHz, VS = +5V, ±10V input range, using internal reference, unless otherwise noted. FREQUENCY SPECTRUM (8192 Point FFT; fIN = 9.
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TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, fS = 40kHz, VS = +5V, ±10V input range, using internal reference, unless otherwise noted. ILE AND DLE AT +25°C 0.1 0.1 ILE (LSB) 0.2 0 –0.1 0 –0.1 –0.2 –0.2 0.2 0.2 0.1 0.1 DLE (LSB) DLE (LSB) ILE (LSB) ILE AND DLE AT –40°C 0.2 0 –0.1 –0.2 800h C00h 000h 400h 0 –0.1 –0.2 800h 7FFh C00h Hex BTC Code 7FFh 1 0.1 Linearity Degradation (LSB/LSB) ILE (LSB) 0.2 0 –0.1 –0.2 0.
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BASIC OPERATION EXTERNAL DATACLK Figure 1b shows a basic circuit to operate the ADS7812 with a ±10V input range. To begin a conversion, a falling edge must be provided to the CONV input. BUSY will go LOW indicating that a conversion has started and will stay LOW until the conversion is complete. Just prior to BUSY rising near the end of the conversion, the internal working register holding the conversion result will be transferred to the internal shift register.
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SYMBOL DESCRIPTION t1 Conversion Plus Acquisition Time 25 µs t2 CONV LOW to All Digital Inputs Stable 8 µs STARTING A CONVERSION MIN TYP MAX UNITS t3 CONV LOW to Initiate a Conversion 40 ns t4 BUSY Rising to Any Digital Input Active 0 ns t5 CONV HIGH Prior to Start of Conversion 2 µs t6 BUSY LOW 15 20 µs t7 CONV LOW to BUSY LOW 85 120 ns t8 Aperture Delay 40 t9 Conversion Time 14 20 µs t10 Conversion Complete to BUSY Rising 1.
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DESCRIPTION DIGITAL OUTPUT ANALOG INPUT BINARY TWO’S COMPLEMENT ±10V 4.88mV 0.5V to 4.5V 0.98mV 9.99512V 0V Full-Scale Range Least Significant Bit (LSB) +Full Scale –1LSB BINARY CODE HEX CODE 4.49902V 0111 1111 1111 7FF 2.5V 0000 0000 0000 000 –4.88mV 2.49902 V 1111 1111 1111 FFF –10V 0.5V 1000 0000 0000 800 Midscale Midscale –1LSB –Full Scale TABLE III. Ideal Input Voltage and Corresponding Digital Output for Two Common Input Ranges.
PAGE 10
INTERNAL DATACLK With EXT/INT tied LOW, the result from conversion ‘n’ is serially transmitted during conversion ‘n+1’, as shown in Figure 5 and with the timing given in Table II. Serial transmission of data occurs only during a conversion. When a transmission is not in progress, DATA and DATACLK are LOW. During the conversion, the results of the previous conversion will be transmitted via DATA, while DATACLK provides the synchronous clock for the serial data.
PAGE 11
External DATACLK Active After the Conversion The preferred method of obtaining the conversion result is to provide the DATACLK signal after the conversion has been completed and before the next conversion starts—as shown in Figure 6. Note that the DATACLK signal should be static before the start of the next conversion. If this is not observed, the DATACLK signal could affect the voltage that is acquired. might be possible to use the rising edge of the DATACLK signal.
PAGE 12
External DATACLK Active After the Conversion and During the Next Conversion Figure 8 shows a method that is a hybrid of the two previous approaches. This method works very well for microcontrollers that do serial transfers 8 bits at a time and for slower microcontrollers.
PAGE 13
The other three input ranges involve the connection at R2IN being driven below GND – 0.3V. This input has a reversebiased ESD protection diode connection to ground. If R2IN is taken below ground, this diode will be forward-biased and will clamp the negative input at –0.4V to –0.7V, depending on the temperature. Here again, these ranges can still be used at the cost of the full-scale range of the converter. Note that Table IV assumes that the voltage at the REF pin is 2.5V.
PAGE 14
CAP The CAP pin is used to compensate the internal reference buffer. A 1µF tantalum capacitor in parallel with a 0.01µF ceramic capacitor should be connected between this pin and ground, with the ceramic capacitor placed as close as possible to the ADS7812. The total value of the capacitance on the CAP pin is critical to optimum performance of the ADS7812. A value larger than 2.0µF could overcompensate the buffer while a value lower than 0.5µF may not provide adequate compensation.
PAGE 15
LAYOUT For example, the timing diagram in Figure 2 shows that the CONV signal should return HIGH sometime during time t2. In fact, the CONV signal can return HIGH at any time during the conversion. However, after time t2, the transition of the CONV signal has the potential of creating a good deal of noise on the ADS7812 die. If this transition occurs at just precisely the wrong time, the conversion results could be affected.
PAGE 16
Keep in mind that the time period when the comparator is most sensitive to noise is fairly small. Also, the peak portion of the noise “event” produced by a digital transition is fairly brief as most digital signals transition in a few nanoseconds. The subsequent noise may last for a period of time longer than this and may induce further effects which require a longer settling time; however, in general, the event is over within a few tens of nanoseconds.
PAGE 17
the DSP56002 must be programmed to enable the serial interface when a LOW to HIGH transition on SCI occurs. The DSP56002 can also provide the CONV signal, as shown in Figure 17. The receive and transmit sections of the interface are decoupled (asynchronous mode) and the transmit section is set to generate a word length frame sync every other transmit frame (frame rate divider set to 2). The prescale modulus should be set to produce a transmit frame at twice the desired conversion rate.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 6-Jun-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS7812UB/1K Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.7 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7812UB/1K SOIC DW 16 1000 367.0 367.0 38.
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