Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External VSSOP 8

12-Bit, Sampling A/D Converter

with I

™

INTERFACE

FEATURES

● 50kHz SAMPLING RATE

● NO MISSING CODES

● 2.7V TO 5V OPERATION

● FOUR-WORD FILO

● A0, A1 ADDRESS PINS

● I

C INTERFACE SUPPORTS:

Standard, Fast, and High-Speed Modes

● MSOP-8 PACKAGE

APPLICATIONS

● VOLTAGE SUPPLY MONITORING

● ISOLATED DATA ACQUISITION

● TRANSDUCER INTERFACE

● BATTERY-OPERATED SYSTEMS

● REMOTE DATA ACQUISITION

DESCRIPTION

The ADS7823 is a single-supply, low-power, 12-bit data

acquisition device that features a serial I

C interface. The

Analog-to-Digital (A/D) converter features a sample-and-

hold amplifier and internal, asynchronous clock. The combi-

nation of an I

C serial two-wire interface and micropower

consumption makes the ADS7823 ideal for applications

requiring the A/D converter to be close to the input source in

remote locations and for applications requiring isolation. The

ADS7823 is available in an MSOP-8 package.

SAR

Serial

Interface

SDA

Comparator

S/H Amp

SCL

REF

CDAC

ADS7823

SBAS180B – JUNE 2001 - REVISED SEPTEMBER 2003

www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

All trademarks are the property of their respective owners.

Summary of content (19 pages)

PAGE 1
ADS7823 SBAS180B – JUNE 2001 - REVISED SEPTEMBER 2003 12-Bit, Sampling A/D Converter with I2C™ INTERFACE DESCRIPTION FEATURES ● ● ● ● ● ● 50kHz SAMPLING RATE NO MISSING CODES 2.7V TO 5V OPERATION FOUR-WORD FILO A0, A1 ADDRESS PINS I2C INTERFACE SUPPORTS: Standard, Fast, and High-Speed Modes ● MSOP-8 PACKAGE The ADS7823 is a single-supply, low-power, 12-bit data acquisition device that features a serial I2C interface.
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ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +VDD to GND ........................................................................ –0.3V to +6V Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V Analog Input Voltage to GND ........................................... –0.3V to +6.0V Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range .........................................
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ELECTRICAL CHARACTERISTICS: +2.7V (Cont.) At TA = –40°C to +85°C, +VDD = +2.7V, VREF = +2.5V, SCL Clock Frequency = 3.4MHz (High Speed Mode) unless otherwise noted. ADS7823E PARAMETER DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOL Input Leakage: IIH IIL Data Format CONDITIONS MIN Power Dissipation Powerdown Mode w/Wrong Address Selected Full Powerdown ADS7823EB MAX MIN +VDD + 0.5 +VDD • 0.3 0.4 10 ✻ ✻ At min 3mA Sink Current VIH = +VDD +0.5 VIL = -0.
PAGE 4
ELECTRICAL CHARACTERISTICS: +5V (Cont.) At TA = –40°C to +85°C, +VDD = +5.0V, VREF = +5.0V, SCL Clock Frequency = 3.4MHz (High Speed Mode) unless otherwise noted. ADS7823E PARAMETER CONDITIONS DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOL Input Leakage: IIH IIL Data Format MIN MIN +VDD + 0.5 +VDD • 0.3 0.4 10 ✻ ✻ Specified Performance High Speed Mode: SCL= 3.
PAGE 5
TIMING CHARACTERISTICS(1) At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted. PARAMETER SYMBOL CONDITIONS SCL Clock Frequency fSCL Standard Mode Fast Mode High-Speed Mode, CB = 100pF max High-Speed Mode, CB = 400pF max Bus Free Time Between a STOP and START Condition tBUF Standard Mode Fast Mode 4.7 1.3 µs µs Hold Time (Repeated) START Condition tHD;STA Standard Mode Fast Mode High-Speed Mode 4.
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TYPICAL CHARACTERISTICS At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT, fIN = 1kHz, 0dB) INTEGRAL LINEARITY ERROR vs CODE (+25°C) 1.00 0 0.75 ILE (LSBS) Amplitude (dB) 0.50 –40 0.25 0 –0.25 –80 –0.50 –0.75 –1.00 000H –120 0 10 20 25 800H Frequency (kHz) DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) CHANGE IN OFFSET vs TEMPERATURE 1.00 1.5 0.75 Delta from +25°C (LSB) 1.0 DLE (LSBS) 0.50 0.25 0 –0.25 –0.
PAGE 7
TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted.
PAGE 8
THEORY OF OPERATION REFERENCE INPUT The external reference sets the analog input range. The ADS7823 will operate with a reference in the range of 50mV to VDD. There are several important implications of this. The ADS7823 is a classic Successive Approximation Register (SAR) A/D converter. The architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µ CMOS process.
PAGE 9
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
PAGE 10
ADDRESS BYTE COMMAND BYTE MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB 1 0 0 1 0 A1 A0 R/W 0 0 0 X X X X X The address byte is the first byte received following the START condition from the master device. The first five bits (MSBs) of the slave address are factory pre-set to 10010. The next two bits of the address byte are the device select bits, A1 and A0. Input pins (A1-A0) on the ADS7823 determine these two bits of the device address for a particular ADS7823.
PAGE 11
READING DATA acknowledge after the fourth data word has been read. This tells the ADS7823 that no further reads will be performed. No more than four data words should be read at a time; further reads will return undefined data. Data can be read from the ADS7823 by read-addressing the part (LSB of address byte set to 1) and receiving the transmitted bytes. Converted data can only be read from the ADS7823 once a conversion has been initiated as described in the preceding section.
PAGE 12
TERMINATING A CONVERSION There are three methods to terminate the conversion of the A/D converter in the ADS7823 after the master initiates conversion: 1) In normal operation sequence (see Figures 3 and 4). The conversion is terminated after the read-addressing has been received. 2) A STOP condition will always terminate a conversion. It will also terminate the HS mode returning the ADS7823 to the F/S mode. 3) A not-acknowledge by the ADS7823 following a second command byte will end a conversion.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Jan-2013 Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7823E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7823E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7823EB/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7823E/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7823E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 ADS7823EB/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7823EB/2K5 VSSOP DGK 8 2500 367.0 367.0 35.
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