Datasheet

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ADS7825

CDAC

6kΩ

Internal

+2.5V Ref

Clock

BUSY

DATACLK

SDATA



D7-D0

BYTE

R/C

CS



PWRD

Successive Approximation Register

and Control Logic

Serial

Data

Out

or

Parallel

Data

Out

Comparator

Buffer

Continuous Conversion

Channel

REF

CAP

A0CONTC A1

40kΩ

AIN

40kΩ

AIN

40kΩ

AIN

40kΩ

AIN

20kΩ 8kΩ

4 Channel, 16-Bit Sampling CMOS A/D Converter

FEATURES

● 25µs max SAMPLING AND CONVERSION

● SINGLE +5V SUPPLY OPERATION

● PIN-COMPATIBLE WITH 12-BIT ADS7824

● PARALLEL AND SERIAL DATA OUTPUT

● 28-PIN 0.3" PLASTIC DIP AND SOIC

●

±2.0 LSB max INL

● 50mW max POWER DISSIPATION

● 50µW POWER DOWN MODE

●

±10V INPUT RANGE, FOUR CHANNEL

MULTIPLEXER

● CONTINUOUS CONVERSION MODE

ADS7825

DESCRIPTION

The ADS7825 can acquire and convert 16 bits to

within ±2.0 LSB in 25µs max while consuming only

50mW max. Laser-trimmed scaling resistors provide

the standard industrial ±10V input range and channel-

to-channel matching of ±0.1%. The ADS7825 is a

low-power 16-bit sampling A/D with a four channel

input multiplexer, S/H, clock, reference, and a

parallel/serial microprocessor interface. It can be con-

figured in a continuous conversion mode to sequen-

tially digitize all four channels. The 28-pin ADS7825

is available in a plastic 0.3" DIP and in a SOIC, both

fully specified for operation over the industrial –40°C

to +85°C range.

ADS7825

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

www.burr-brown.com/databook/ADS7825.html

1996 Burr-Brown Corporation PDS-1304B Printed in U.S.A. October, 1997

SBAS045

Summary of content (21 pages)

PAGE 1
® ADS ADS7825 782 5 ADS 782 5 www.burr-brown.com/databook/ADS7825.html 4 Channel, 16-Bit Sampling CMOS A/D Converter FEATURES DESCRIPTION ● 25µs max SAMPLING AND CONVERSION ● SINGLE +5V SUPPLY OPERATION The ADS7825 can acquire and convert 16 bits to within ±2.0 LSB in 25µs max while consuming only 50mW max. Laser-trimmed scaling resistors provide the standard industrial ±10V input range and channelto-channel matching of ±0.1%.
PAGE 2
SPECIFICATIONS ELECTRICAL At TA = –40°C to +85°C, f S = 40kHz, VS1 = VS2 = VS = +5V ±5%, using external reference, CONTC = 0V, unless otherwise specified.
PAGE 3
SPECIFICATIONS (CONT) ELECTRICAL At TA = –40°C to +85°C, fS = 40kHz, VS1 = VS2 = V S = +5V ±5%, using external reference, CONTC = 0V, unless otherwise specified. ADS7825P, U PARAMETER CONDITIONS DIGITAL TIMING Bus Access Time Bus Relinquish Time Data Clock Internal Clock (Output only when transmitting data) External Clock MIN TYP ADS7825PB, UB MAX MIN TYP MAX UNITS ✻ ✻ ns ns PAR/SER = +5V PAR/SER = +5V PAR/SER = 0V EXT/INT LOW 0.5 1.5 ✻ ✻ MHz EXT/INT HIGH 0.1 10 ✻ ✻ MHz +5.
PAGE 4
PIN ASSIGNMENTS PIN # NAME 1 AGND1 I/O DESCRIPTION 2 AIN0 Analog Input Channel 0. Full-scale input range is ±10V. 3 AIN 1 Analog Input Channel 1. Full-scale input range is ±10V. 4 AIN 2 Analog Input Channel 2. Full-scale input range is ±10V. 5 AIN 3 Analog Input Channel 3. Full-scale input range is ±10V. 6 CAP Internal Reference Output Buffer. 2.2µF Tantalum to ground. 7 REF Reference Input/Output. Outputs +2.5V nominal.
PAGE 5
TYPICAL PERFORMANCE CURVES At TA = +25°C, fS = 40kHz, VS1 = VS2 = +5V, using internal reference, unless otherwise noted. CROSSTALK vs INPUT FREQUENCY (Active Channel Amplitude = –0.1dB) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 Resulting Amplitude on Selected Channel (dB) (Input Grounded) Amplitude (dB) FREQUENCY SPECTRUM (8192 Point FFT; fIN = 1.02kHz, –0.5dB) 0 5 10 Frequency (kHz) 15 20 –60.0 –70.0 Adjacent Channels, Worst Pair –80.0 –90.0 Adjacent Channels –100.
PAGE 6
TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, fS = 40kHz, VS1 = VS2 = +5V, using internal reference, unless otherwise noted. –110 105 –105 SFDR 100 16-Bit LSBs 110 –100 95 –95 SNR THD 90 –25 –85 0 25 All Codes INL 8192 16384 24576 32768 40960 49152 57344 65535 49152 57344 65535 Decimal Code –90 SINAD 80 –50 3 2 1 0 –1 –2 –3 0 50 75 16-Bit LSBs 85 THD (dB) SFDR, SINARD, and SNR (dB) A. C. PARAMETERS vs TEMPERATURE (fIN = 1kHz, –0.
PAGE 7
BASIC OPERATION SERIAL OUTPUT Figure 1b shows a basic circuit to operate the ADS7825 with serial output (Channel 0 selected). Taking R/C (pin 22) LOW for 40ns (12µs max) will initiate a conversion and output valid data from the previous conversion on SDATA (pin 16) synchronized to 16 clock pulses output on DATACLK (pin 15). BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the serial data has been transmitted.
PAGE 8
STARTING A CONVERSION The combination of CS (pin 23) and R/C (pin 22) LOW for a minimum of 40ns places the sample/hold of the ADS7825 in the hold state and starts conversion ‘n’. BUSY (pin 24) will go LOW and stay LOW until conversion ‘n’ is completed and the internal output register has been updated. All new convert commands during BUSY LOW will be ignored. CS and/or R/C must go HIGH before BUSY goes HIGH or a new conversion will be initiated without sufficient time to acquire a new signal.
PAGE 9
t1 t1 R/C t3 t3 t4 BUSY t5 t6 t6 t7 Convert Acquire MODE t8 t12 Acquire Convert t12 t11 t10 Parallel Data Bus Previous High Byte Valid Previous High Byte Valid Hi-Z Previous Low Byte Valid Low Byte Valid High Byte Valid Not Valid High Byte Valid t9 t2 t12 t12 t9 Hi-Z t12 t12 BYTE FIGURE 2. Conversion Timing with Parallel Output (CS LOW).
PAGE 10
® ADS7825 10 t21 t3 t1 t27 t21 t17 t19 t23 t20 1 t17 Tag 0 t24 2 Tag 1 Bit 15 (MSB) 3 Tag 2 Bit 14 4 FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT HIGH). Read After Conversion.
PAGE 11
ADS7825 ® t21 t3 t17 t1 t19 t20 t27 t23 Tag 0 t17 t24 Tag 1 Bit 15 (MSB) t11 Tag 16 Bit 0 (LSB) Tag 17 Tag 0 t22 t28 FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT HIGH). Read During Conversion (Previous Conversion Results).
PAGE 12
READING DATA after the start of conversion ‘n’. Do not attempt to read data beyond 12µs after the start of conversion ‘n’ until BUSY (pin 24) goes HIGH; this may result in reading invalid data. Refer to Table II and Figures 2 and 3 for timing constraints. PARALLEL OUTPUT To use the parallel output, tie PAR/SER (pin 20) HIGH. The parallel output will be active when R/C (pin 22) is HIGH and CS (pin 23) is LOW. Any other combination of CS and R/C will tri-state the parallel output.
PAGE 13
DATACLK (pin 15). The data will be valid on both the rising and falling edges of the internal data clock. The rising edge of BUSY (pin 24) can be used to latch the data. After the 16th clock pulse, DATACLK will remain LOW until the next conversion is initiated, while SDATA will go to whatever logic level was input on TAG (pin 17) during the first clock pulse. The SDATA output will tri-state when BUSY returns HIGH. Refer to Table II and Figure 4 for timing information.
PAGE 14
into the A0 and A1 registers (pins 19 and 18, respectively) prior to CONTC being raised HIGH, becomes the first address in the sequential continuous conversion mode (e.g., if Channel 1 was the last address selected then Channel 2 will follow, then Channel 3, and so on). The A0 and A1 address inputs become outputs when the device is in this mode.
PAGE 15
CDAC. Capacitor values larger than 2.2µF will have little affect on improving performance. CALIBRATION The ADS7825 has no internal provision for correcting the individual bipolar zero error or full-scale error for each individual channel. Instead, the bipolar zero error of each channel is guaranteed to be below a level which is quite small for a 16-bit converter with a ±10V input range (slightly more than ±32 LSBs). In addition, the channel errors should match each other to within 16 LSBs.
PAGE 16
SIGNAL CONDITIONING The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The amount of charge injection due to the sampling FET switch on the ADS7825 is approximately 5-10% of the amount on similar ADCs with the charge redistribution DAC (CDAC) architecture. There is also a resistive front end which attenuates any charge which is released.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.
PAGE 18
PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2010 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7825U/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 ADS7825UB/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7825U/1K SOIC DW 28 1000 346.0 346.0 49.0 ADS7825UB/1K SOIC DW 28 1000 346.0 346.0 49.
PAGE 21
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