Datasheet

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t
CYC
Power
Down
t
SU(CS)
t
CSD
Hi-Z
Null
Bit
B11
(MSB)
B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
1
Null
Bit
B11 B10 B9 B8
Hi-Z
t
SMPL
t
CONV
t
DATA
CS
/SHDN
DCLOCK
D
OUT
t
CYC
Power
Down
t
SU(CS)
t
CSD
Hi-Z
Null
Bit
B9
(MSB)
B8 B4 B3 B2 B1 B0
1
Null
Bit
MSB
Hi-Z
CS
/SHDN
DCLOCK
D
OUT
Hi-Z
Null
Bit
B7
(MSB)
B6 B4 B3 B2 B1 B0
1
Null
Bit
MSB
Hi-Z
t
SMPL
t
CONV
ADS7826
D
OUT
ADS7827
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
Serial Interface
SINAD = 6.02 × ENOB + 1.76
The ADS7826/27/29 family communicates with
With lower reference voltages, extra care should be
microprocessors and other digital systems via a
taken to provide a clean layout including adequate
synchronous 3-wire serial interface. Timings for
bypassing, a clean power supply, a low-noise
ADS7829 are shown in Figure 36 and Table 1. The
reference, and a low-noise input signal. Because the
DCLOCK signal synchronizes the data transfer with
LSB size is lower, the converter is more sensitive to
each bit being transmitted on the falling edge of
external sources of error such as nearby digital
DCLOCK. Most receiving systems capture the
signals and electromagnetic interference.
bitstream on the rising edge of DCLOCK. However, if
DIGITAL INTERFACE the minimum hold time for D
OUT
is acceptable, the
system can use the falling edge of DCLOCK to
Signal Levels
capture each bit.
The digital inputs of the ADS7826/27/29 family can
The timings for ADS7826 and ADS7827 serial
accommodate logic levels up to 6 V regardless of the
interface are shown in Figure 37 and Table 1. The
value of V
CC
. Thus, the ADS7826/27/29 family can be
DCLOCK signal synchronizes the data transfer with
powered at 3 V and still accept inputs from logic
each bit being transmitted on the falling edge of
powered at 5 V.
DCLOCK. Most receiving systems capture the
bitstream on the rising edge of DCLOCK. However, if
The CMOS digital output (D
OUT
) swings 0 V to V
CC
. If
the minimum hold time for D
OUT
is acceptable, athe
V
CC
is 3 V and this output is connected to a 5-V
system can use the fallng edge of DCLOCK to
CMOS logic input, then that IC may require more
capture each bit.
supply current than normal and may have a slightly
longer propagation delay.
After completing the data transfer, if further clocks are applied with CS LOW, the A/D outputs LSB-First data then
followed with zeroes indefinitely.
Figure 36. ADS7829 Timing
Figure 37. ADS7826 and ADS7827 Timing
14