Datasheet

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D
OUT
1.4 V
Test Point
3 k
100 pF
C
LOAD
t
r
D
OUT
t
f
Test Point
3 k
CS/SHDN
D
OUT
D
OUT
90%
10%
1
B11
2
CS/SHDN
DCLOCK
D
OUT
DCLOCK
V
IL
100 pF
Voltage Waveforms for t
en
D
OUT
t
h(DO)
Voltage Waveforms for D
OUT
Delay Times, t
dDO
V
OH
V
OL
V
OH
V
OL
D
OUT
t
h(DO)
C
LOAD
V
CC
t
dis
Waveform 2, t
en
t
dis
Waveform 1
Load Circuit for t
dis
and t
en
t
dis
V
IH
Voltage Waveforms for t
dis
Waveform 1
(1)
Waveform 2
(2)
t
en
V
OL
Load Circuit for t
dDO
, t
r
, and t
f
Voltage Waveforms for D
OUT
Rise and Fall Times, t
r
, t
f
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
(1)
Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control.
(2)
Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control.
Figure 38. Timing Diagrams and Test Circuits for the Parameters in Table 1.
POWER DISSIPATION
The architecture of the converter, the semiconductor This way, the converter spends the longest possible
fabrication process, and a careful design allows the time in the power down mode. This is very important
ADS7826/27/29 family to convert at the full sample as the converter not only uses power on each
rate while requiring very little power. But, for the DCLOCK transition (as is typical for digital CMOS
absolute lowest power dissipation, there are several components) but also uses some current for the
things to keep in mind. analog circuitry, such as the comparator. The analog
section dissipates power continuously, until the
The power dissipation of the ADS7826/27/29 family
power-down mode is entered.
scales directly with conversion rate. Therefore, the
first step to achieving the lowest power dissipation is The current consumption of the ADS7826/27/29
to find the lowest conversion rate that satisfies the family versus sample rate. For this graph, the
requirements of the system. converter is clocked at maximum DCLOCK rate
regardless of the sample rate —CS is HIGH for the
In addition, the ADS7826/27/29 family is in power
remaining sample period. Figure 4 also shows current
down mode under two conditions: when the
consumption versus sample rate. However, in this
conversion is complete and whenever CS is HIGH.
case, the minimum DCLOCK cylce time is used—CS
Ideally, each conversion occurs as quickly as
is HIGH for one DCLOCK cycle.
possible, preferably, at DCLOCK rate.
16